1 From a10d0b8516bc3f48f0c1005f8e69efce12cea8f9 Mon Sep 17 00:00:00 2001
2 From: Sandor Yu <Sandor.yu@nxp.com>
3 Date: Mon, 23 Sep 2019 09:09:38 +0800
4 Subject: [PATCH] drm: imx: hdmi: support arc function
6 Add HDMI ARC configurate function.
8 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
10 drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c | 59 +++++++++++++++++++++++++++++++++
11 1 file changed, 59 insertions(+)
13 --- a/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
14 +++ b/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
15 @@ -192,6 +192,62 @@ static const struct hdmi_pll_tuning imx8
16 { 7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680, 0x04F, 0, 0, 0 }
19 +static void hdmi_arc_config(struct cdns_mhdp_device *mhdp)
21 + u16 txpu_calib_code;
22 + u16 txpd_calib_code;
23 + u16 txpu_adj_calib_code;
24 + u16 txpd_adj_calib_code;
25 + u16 prev_calib_code;
30 + cdns_phy_reg_write(mhdp, TXDA_CYA_AUXDA_CYA, 0x0001);
32 + prev_calib_code = cdns_phy_reg_read(mhdp, TX_DIG_CTRL_REG_2);
33 + txpu_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPUCAL_CTRL);
34 + txpd_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPDCAL_CTRL);
35 + txpu_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPU_ADJ_CTRL);
36 + txpd_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPD_ADJ_CTRL);
38 + new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
39 + + txpu_adj_calib_code + txpd_adj_calib_code;
41 + if (new_calib_code != prev_calib_code) {
42 + rdata = cdns_phy_reg_read(mhdp, TX_ANA_CTRL_REG_1);
44 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata);
45 + cdns_phy_reg_write(mhdp, TX_DIG_CTRL_REG_2, new_calib_code);
48 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata);
52 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0100);
54 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0300);
56 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_3, 0x0000);
58 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2008);
60 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2018);
62 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2098);
63 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030C);
64 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_5, 0x0010);
66 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_4, 0x4001);
68 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2198);
70 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030D);
72 + cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030F);
75 static void hdmi_phy_set_vswing(struct cdns_mhdp_device *mhdp)
77 const u32 num_lanes = 4;
78 @@ -604,6 +660,9 @@ static int hdmi_phy_power_up(struct cdns
83 + hdmi_arc_config(mhdp);
85 /* Configure PHY in A0 mode (PHY must be in the A0 power
86 * state in order to transmit data)