1 From 8e4cbfc8b1b86479a4bc64d6034449096d0af3a1 Mon Sep 17 00:00:00 2001
2 From: Sandor Yu <Sandor.yu@nxp.com>
3 Date: Thu, 26 Sep 2019 17:00:26 +0800
4 Subject: [PATCH] drm: imx: mhdp: add dual mode support for imx8qm
6 Add dual mode support for imx8qm.
7 imx8qm hdmi/dp driver are ready to support 4K.
9 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
11 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 4 ----
12 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 6 -----
13 drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c | 30 +++++++++++++++++++------
14 drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c | 3 +--
15 drivers/gpu/drm/imx/cdns-mhdp-imx.h | 14 +-----------
16 5 files changed, 25 insertions(+), 32 deletions(-)
18 --- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
19 +++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
20 @@ -118,9 +118,6 @@ static void cdns_dp_mode_set(struct cdns
22 memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
25 -// mhdp->dual_mode = video_is_dual_mode(mode);
27 dp_pixel_clk_reset(mhdp);
29 cdns_mhdp_plat_call(mhdp, pclk_rate);
30 @@ -450,7 +447,6 @@ static int __cdns_dp_probe(struct platfo
32 cdns_mhdp_plat_call(mhdp, power_on);
34 -// mhdp->dual_mode = false;
35 cdns_mhdp_plat_call(mhdp, firmware_init);
37 /* DP FW alive check */
38 --- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
39 +++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
40 @@ -343,9 +343,6 @@ static void cdns_hdmi_bridge_mode_set(st
42 memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
45 -// hdmi->dual_mode = video_is_dual_mode(mode);
47 hdmi_lanes_config(mhdp);
49 cdns_mhdp_plat_call(mhdp, pclk_rate);
50 @@ -446,9 +443,6 @@ static int __cdns_hdmi_probe(struct plat
54 - /* Initialize dual_mode to false */
55 -// hdmi->dual_mode = false;
57 cdns_mhdp_plat_call(mhdp, power_on);
60 --- a/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
61 +++ b/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
64 #include "cdns-mhdp-imx.h"
66 +#define PLL_800MHZ (800000000)
68 +#define HDP_DUAL_MODE_MIN_PCLK_RATE 300000 /* KHz */
69 +#define HDP_SINGLE_MODE_MAX_WIDTH 1920
71 #define CSR_PIXEL_LINK_MUX_CTL 0x00
72 #define CSR_PIXEL_LINK_MUX_VCP_OFFSET 5
73 #define CSR_PIXEL_LINK_MUX_HCP_OFFSET 4
75 -#define PLL_800MHZ (800000000)
76 +static bool imx8qm_video_dual_mode(struct cdns_mhdp_device *mhdp)
78 + struct drm_display_mode *mode = &mhdp->mode;
79 + return (mode->clock > HDP_DUAL_MODE_MIN_PCLK_RATE ||
80 + mode->hdisplay > HDP_SINGLE_MODE_MAX_WIDTH) ? true : false;
83 static void imx8qm_pixel_link_mux(struct imx_mhdp_device *imx_mhdp)
85 struct drm_display_mode *mode = &imx_mhdp->mhdp.mode;
89 + dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
92 - if (imx_mhdp->dual_mode)
94 val |= 0x2; /* pixel link 0 and 1 are active */
95 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
96 val |= 1 << CSR_PIXEL_LINK_MUX_VCP_OFFSET;
97 @@ -276,12 +289,13 @@ static void imx8qm_pixel_clk_disable(str
99 static void imx8qm_pixel_clk_set_rate(struct imx_mhdp_device *imx_mhdp, u32 pclock)
101 + bool dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
102 struct imx_hdp_clks *clks = &imx_mhdp->clks;
104 /* pixel clock for HDMI */
105 clk_set_rate(clks->av_pll, pclock);
107 - if (imx_mhdp->dual_mode == true) {
108 + if (dual_mode == true) {
109 clk_set_rate(clks->clk_pxl, pclock/2);
110 clk_set_rate(clks->clk_pxl_link, pclock/2);
112 @@ -471,18 +485,20 @@ void cdns_mhdp_plat_init_imx8qm(struct c
114 struct imx_mhdp_device *imx_mhdp =
115 container_of(mhdp, struct imx_mhdp_device, mhdp);
116 + bool dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
118 - imx8qm_pixel_link_sync_disable(imx_mhdp->dual_mode);
119 - imx8qm_pixel_link_invalid(imx_mhdp->dual_mode);
120 + imx8qm_pixel_link_sync_disable(dual_mode);
121 + imx8qm_pixel_link_invalid(dual_mode);
124 void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp)
126 struct imx_mhdp_device *imx_mhdp =
127 container_of(mhdp, struct imx_mhdp_device, mhdp);
128 + bool dual_mode = imx8qm_video_dual_mode(&imx_mhdp->mhdp);
130 - imx8qm_pixel_link_valid(imx_mhdp->dual_mode);
131 - imx8qm_pixel_link_sync_enable(imx_mhdp->dual_mode);
132 + imx8qm_pixel_link_valid(dual_mode);
133 + imx8qm_pixel_link_sync_enable(dual_mode);
136 void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp)
137 --- a/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
138 +++ b/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
139 @@ -172,7 +172,6 @@ static int cdns_mhdp_imx_bind(struct dev
141 drm_encoder_cleanup(encoder);
143 - imx_mhdp->dual_mode = false;
147 @@ -205,7 +204,7 @@ static struct platform_driver cdns_mhdp_
148 .probe = cdns_mhdp_imx_probe,
149 .remove = cdns_mhdp_imx_remove,
151 - .name = "cdn-hdp-imx8qm",
152 + .name = "cdns-mhdp-imx",
153 .of_match_table = cdns_mhdp_imx_dt_ids,
156 --- a/drivers/gpu/drm/imx/cdns-mhdp-imx.h
157 +++ b/drivers/gpu/drm/imx/cdns-mhdp-imx.h
159 #include <drm/drm_encoder_slave.h>
162 -#define HDP_DUAL_MODE_MIN_PCLK_RATE 300000 /* KHz */
163 -#define HDP_SINGLE_MODE_MAX_WIDTH 1920
165 -static inline bool video_is_dual_mode(const struct drm_display_mode *mode)
167 - return (mode->clock > HDP_DUAL_MODE_MIN_PCLK_RATE ||
168 - mode->hdisplay > HDP_SINGLE_MODE_MAX_WIDTH) ? true : false;
171 struct imx_mhdp_device;
173 struct imx_hdp_clks {
174 @@ -62,17 +53,14 @@ struct imx_mhdp_device {
180 struct device *pd_mhdp_dev;
181 struct device *pd_pll0_dev;
182 struct device *pd_pll1_dev;
183 struct device_link *pd_mhdp_link;
184 struct device_link *pd_pll0_link;
185 struct device_link *pd_pll1_link;
190 void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp);
191 void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp);
192 void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp);