target/linux/layerscape/patches-5.4/812-pcie-0011-PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch

   1 From 7e92994ec22c9d337f6012ac913e7958012ad52e Mon Sep 17 00:00:00 2001
   2 From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
   3 Date: Tue, 25 Jun 2019 09:09:28 +0000
   4 Subject: [PATCH] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
   5
   6 There are some 8-bit and 16-bit registers in PCIe configuration
   7 space, so add these accessors accordingly.
   8
   9 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  10 Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
  11 Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
  12 ---
  13  drivers/pci/controller/mobiveil/pcie-mobiveil.h | 20 ++++++++++++++++++++
  14  1 file changed, 20 insertions(+)
  15
  16 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
  17 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
  18 @@ -182,9 +182,29 @@ static inline u32 csr_readl(struct mobiv
  19         return csr_read(pcie, off, 0x4);
  20  }
  21
  22 +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
  23 +{
  24 +       return csr_read(pcie, off, 0x2);
  25 +}
  26 +
  27 +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
  28 +{
  29 +       return csr_read(pcie, off, 0x1);
  30 +}
  31 +
  32  static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
  33  {
  34         csr_write(pcie, val, off, 0x4);
  35  }
  36
  37 +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
  38 +{
  39 +       csr_write(pcie, val, off, 0x2);
  40 +}
  41 +
  42 +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
  43 +{
  44 +       csr_write(pcie, val, off, 0x1);
  45 +}
  46 +
  47  #endif /* _PCIE_MOBIVEIL_H */