1 From 21d86ac5a6c0ede443676cb455e988adcc0e3762 Mon Sep 17 00:00:00 2001
2 From: Xiaowei Bao <xiaowei.bao@nxp.com>
3 Date: Sat, 5 Jan 2019 16:06:43 +0800
4 Subject: [PATCH] PCI: mobiveil: Add the EP driver support
6 Add the EP driver support for Mobiveil base on endpoint framework.
8 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
9 [Zhiqiang: Correct the Copyright]
10 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
13 drivers/pci/controller/mobiveil/Kconfig | 5 +
14 drivers/pci/controller/mobiveil/Makefile | 1 +
15 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 568 +++++++++++++++++++++
16 drivers/pci/controller/mobiveil/pcie-mobiveil.c | 99 +++-
17 drivers/pci/controller/mobiveil/pcie-mobiveil.h | 68 +++
18 6 files changed, 734 insertions(+), 8 deletions(-)
19 create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
23 @@ -12501,6 +12501,7 @@ F: drivers/ntb/hw/mscc/
24 PCI DRIVER FOR MOBIVEIL PCIE IP
25 M: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
26 M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
27 +M: Xiaowei Bao <xiaowei.bao@nxp.com>
28 L: linux-pci@vger.kernel.org
30 F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
31 --- a/drivers/pci/controller/mobiveil/Kconfig
32 +++ b/drivers/pci/controller/mobiveil/Kconfig
33 @@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
34 depends on PCI_MSI_IRQ_DOMAIN
37 +config PCIE_MOBIVEIL_EP
39 + depends on PCI_ENDPOINT
40 + select PCIE_MOBIVEIL
42 config PCIE_MOBIVEIL_PLAT
43 bool "Mobiveil AXI PCIe controller"
44 depends on ARCH_ZYNQMP || COMPILE_TEST
45 --- a/drivers/pci/controller/mobiveil/Makefile
46 +++ b/drivers/pci/controller/mobiveil/Makefile
48 # SPDX-License-Identifier: GPL-2.0
49 obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
50 obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
51 +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
52 obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
53 obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
55 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
57 +// SPDX-License-Identifier: GPL-2.0
59 + * Mobiveil PCIe Endpoint controller driver
61 + * Copyright 2019 NXP
62 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
65 +#include <linux/of.h>
66 +#include <linux/pci-epc.h>
67 +#include <linux/pci-epf.h>
68 +#include <linux/platform_device.h>
69 +#include "pcie-mobiveil.h"
71 +static void mobiveil_pcie_ep_func_select(struct mobiveil_pcie *pcie, u8 func_no)
76 + * select to access the config space of func_no by setting func_no
77 + * to FUNC_SEL_SHIFT bit of PAB_CTRL register.
79 + func_num = csr_readl(pcie, PAB_CTRL);
80 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
81 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
82 + csr_writel(pcie, func_num, PAB_CTRL);
85 +static void mobiveil_pcie_ep_func_deselect(struct mobiveil_pcie *pcie)
90 + * clear the FUNC_SEL_SHIFT bits when access other registers except
91 + * config space register.
93 + func_num = csr_readl(pcie, PAB_CTRL);
94 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
95 + csr_writel(pcie, func_num, PAB_CTRL);
98 +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
100 + csr_writel(pcie, bar, GPEX_BAR_SELECT);
101 + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
102 + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
105 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
107 + __mobiveil_pcie_ep_reset_bar(pcie, bar);
110 +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
111 + u8 func_no, u8 cap_ptr, u8 cap)
113 + u8 cap_id, next_cap_ptr;
119 + mobiveil_pcie_ep_func_select(pcie, func_no);
121 + reg = csr_readw(pcie, cap_ptr);
122 + cap_id = (reg & 0x00ff);
124 + mobiveil_pcie_ep_func_deselect(pcie);
126 + if (cap_id > PCI_CAP_ID_MAX)
132 + next_cap_ptr = (reg & 0xff00) >> 8;
133 + return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
134 + next_cap_ptr, cap);
137 +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie_ep *ep,
138 + u8 func_no, u8 cap)
140 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
144 + mobiveil_pcie_ep_func_select(pcie, func_no);
146 + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
147 + next_cap_ptr = (reg & 0x00ff);
149 + mobiveil_pcie_ep_func_deselect(pcie);
151 + return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
152 + next_cap_ptr, cap);
155 +static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
156 + struct pci_epf_header *hdr)
158 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
159 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
161 + mobiveil_pcie_ep_func_select(pcie, func_no);
163 + csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
164 + csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
165 + csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
166 + csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
167 + csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
169 + csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
170 + csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
171 + csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
172 + csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
174 + mobiveil_pcie_ep_func_deselect(pcie);
179 +static void mobiveil_pcie_ep_inbound_win(struct mobiveil_pcie_ep *ep,
180 + u8 func_no, enum pci_barno bar,
181 + dma_addr_t cpu_addr)
183 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
185 + program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
188 +static int mobiveil_pcie_ep_outbound_win(struct mobiveil_pcie_ep *ep,
189 + phys_addr_t phys_addr,
190 + u64 pci_addr, u8 func_no,
194 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
196 + free_win = find_first_zero_bit(ep->apio_wins_map, ep->apio_wins);
197 + if (free_win >= ep->apio_wins) {
198 + dev_err(&pcie->pdev->dev, "No free outbound window\n");
202 + program_ob_windows_ep(pcie, func_no, free_win, phys_addr,
203 + pci_addr, MEM_WINDOW_TYPE, size);
205 + set_bit(free_win, ep->apio_wins_map);
206 + ep->apio_addr[free_win] = phys_addr;
211 +static void mobiveil_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
212 + struct pci_epf_bar *epf_bar)
214 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
215 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
216 + enum pci_barno bar = epf_bar->barno;
218 + if (bar < ep->bar_num) {
219 + __mobiveil_pcie_ep_reset_bar(pcie, func_no * ep->bar_num + bar);
221 + mobiveil_pcie_disable_ib_win_ep(pcie, func_no, bar);
225 +static int mobiveil_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
226 + struct pci_epf_bar *epf_bar)
228 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
229 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
230 + enum pci_barno bar = epf_bar->barno;
231 + size_t size = epf_bar->size;
233 + if (bar < ep->bar_num) {
234 + mobiveil_pcie_ep_inbound_win(ep, func_no, bar,
235 + epf_bar->phys_addr);
237 + csr_writel(pcie, func_no * ep->bar_num + bar,
239 + csr_writel(pcie, lower_32_bits(~(size - 1)),
240 + GPEX_BAR_SIZE_LDW);
241 + csr_writel(pcie, upper_32_bits(~(size - 1)),
242 + GPEX_BAR_SIZE_UDW);
248 +static int mobiveil_pcie_find_index(struct mobiveil_pcie_ep *ep,
254 + for (index = 0; index < ep->apio_wins; index++) {
255 + if (ep->apio_addr[index] != addr)
257 + *atu_index = index;
264 +static void mobiveil_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
269 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
270 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
272 + ret = mobiveil_pcie_find_index(ep, addr, &atu_index);
276 + mobiveil_pcie_disable_ob_win(pcie, atu_index);
277 + clear_bit(atu_index, ep->apio_wins_map);
280 +static int mobiveil_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
282 + u64 pci_addr, size_t size)
285 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
286 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
288 + ret = mobiveil_pcie_ep_outbound_win(ep, addr, pci_addr, func_no, size);
290 + dev_err(&pcie->pdev->dev, "Failed to enable address\n");
297 +static int mobiveil_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
299 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
300 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
304 + msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
309 + mobiveil_pcie_ep_func_select(pcie, func_no);
311 + reg = msi_cap + PCI_MSI_FLAGS;
312 + val = csr_readw(pcie, reg);
314 + mobiveil_pcie_ep_func_deselect(pcie);
316 + if (!(val & PCI_MSI_FLAGS_ENABLE))
319 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
324 +static int mobiveil_pcie_ep_set_msi(struct pci_epc *epc,
325 + u8 func_no, u8 interrupts)
327 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
328 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
332 + msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
337 + mobiveil_pcie_ep_func_select(pcie, func_no);
339 + reg = msi_cap + PCI_MSI_FLAGS;
340 + val = csr_readw(pcie, reg);
341 + val &= ~PCI_MSI_FLAGS_QMASK;
342 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
343 + csr_writew(pcie, val, reg);
345 + mobiveil_pcie_ep_func_deselect(pcie);
350 +static int mobiveil_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
352 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
353 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
357 + msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
362 + mobiveil_pcie_ep_func_select(pcie, func_no);
364 + reg = msix_cap + PCI_MSIX_FLAGS;
365 + val = csr_readw(pcie, reg);
367 + mobiveil_pcie_ep_func_deselect(pcie);
369 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
372 + val &= PCI_MSIX_FLAGS_QSIZE;
377 +static int mobiveil_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no,
380 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
381 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
385 + msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
390 + mobiveil_pcie_ep_func_select(pcie, func_no);
392 + reg = msix_cap + PCI_MSIX_FLAGS;
393 + val = csr_readw(pcie, reg);
394 + val &= ~PCI_MSIX_FLAGS_QSIZE;
396 + csr_writew(pcie, val, reg);
398 + mobiveil_pcie_ep_func_deselect(pcie);
403 +static int mobiveil_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
404 + enum pci_epc_irq_type type,
407 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
409 + if (!ep->ops->raise_irq)
412 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
415 +static const struct pci_epc_features*
416 +mobiveil_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
418 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
420 + if (!ep->ops->get_features)
423 + return ep->ops->get_features(ep);
426 +static const struct pci_epc_ops epc_ops = {
427 + .write_header = mobiveil_pcie_ep_write_header,
428 + .set_bar = mobiveil_pcie_ep_set_bar,
429 + .clear_bar = mobiveil_pcie_ep_clear_bar,
430 + .map_addr = mobiveil_pcie_ep_map_addr,
431 + .unmap_addr = mobiveil_pcie_ep_unmap_addr,
432 + .set_msi = mobiveil_pcie_ep_set_msi,
433 + .get_msi = mobiveil_pcie_ep_get_msi,
434 + .set_msix = mobiveil_pcie_ep_set_msix,
435 + .get_msix = mobiveil_pcie_ep_get_msix,
436 + .raise_irq = mobiveil_pcie_ep_raise_irq,
437 + .get_features = mobiveil_pcie_ep_get_features,
440 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no)
442 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
444 + dev_err(&pcie->pdev->dev, "EP cannot trigger legacy IRQs\n");
449 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
452 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
453 + struct pci_epc *epc = ep->epc;
454 + u16 msg_ctrl, msg_data;
455 + u32 msg_addr_lower, msg_addr_upper, reg;
461 + msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
466 + mobiveil_pcie_ep_func_select(pcie, func_no);
468 + reg = msi_cap + PCI_MSI_FLAGS;
469 + msg_ctrl = csr_readw(pcie, reg);
470 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
471 + reg = msi_cap + PCI_MSI_ADDRESS_LO;
472 + msg_addr_lower = csr_readl(pcie, reg);
474 + reg = msi_cap + PCI_MSI_ADDRESS_HI;
475 + msg_addr_upper = csr_readl(pcie, reg);
476 + reg = msi_cap + PCI_MSI_DATA_64;
477 + msg_data = csr_readw(pcie, reg);
479 + msg_addr_upper = 0;
480 + reg = msi_cap + PCI_MSI_DATA_32;
481 + msg_data = csr_readw(pcie, reg);
483 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
485 + mobiveil_pcie_ep_func_deselect(pcie);
487 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
488 + msg_addr, epc->mem->page_size);
492 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
494 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
499 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
502 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
503 + struct pci_epc *epc = ep->epc;
504 + u32 msg_addr_upper, msg_addr_lower;
510 + msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
515 + mobiveil_pcie_ep_func_deselect(pcie);
517 + msg_addr_lower = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
518 + PCI_MSIX_ENTRY_LOWER_ADDR +
519 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
520 + msg_addr_upper = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
521 + PCI_MSIX_ENTRY_UPPER_ADDR +
522 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
523 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
524 + msg_data = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
525 + PCI_MSIX_ENTRY_DATA +
526 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
528 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
529 + msg_addr, epc->mem->page_size);
533 + writel(msg_data, ep->msi_mem);
535 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
540 +void mobiveil_pcie_ep_exit(struct mobiveil_pcie_ep *ep)
542 + struct pci_epc *epc = ep->epc;
544 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
545 + epc->mem->page_size);
547 + pci_epc_mem_exit(epc);
550 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep)
554 + struct pci_epc *epc;
555 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
556 + struct device *dev = &pcie->pdev->dev;
557 + struct device_node *np = dev->of_node;
559 + if (!pcie->csr_axi_slave_base) {
560 + dev_err(dev, "csr_base is not populated\n");
564 + ret = of_property_read_u32(np, "apio-wins", &ep->apio_wins);
566 + dev_err(dev, "Unable to read apio-wins property\n");
570 + if (ep->apio_wins > MAX_IATU_OUT) {
571 + dev_err(dev, "Invalid apio-wins\n");
574 + ep->apio_wins_map = devm_kcalloc(dev,
575 + BITS_TO_LONGS(ep->apio_wins),
578 + if (!ep->apio_wins_map)
581 + addr = devm_kcalloc(dev, ep->apio_wins, sizeof(phys_addr_t),
586 + ep->apio_addr = addr;
588 + mobiveil_pcie_enable_bridge_pio(pcie);
589 + mobiveil_pcie_enable_engine_apio(pcie);
590 + mobiveil_pcie_enable_engine_ppio(pcie);
591 + mobiveil_pcie_enable_msi_ep(pcie);
593 + epc = devm_pci_epc_create(dev, &epc_ops);
595 + dev_err(dev, "Failed to create epc device\n");
596 + return PTR_ERR(epc);
600 + epc_set_drvdata(epc, ep);
602 + ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
604 + epc->max_functions = 1;
606 + if (ep->ops->ep_init)
607 + ep->ops->ep_init(ep);
609 + ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
612 + dev_err(dev, "Failed to initialize address space\n");
616 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
617 + epc->mem->page_size);
618 + if (!ep->msi_mem) {
619 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
625 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
626 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
627 @@ -168,18 +168,12 @@ void program_ib_windows(struct mobiveil_
629 * routine to program the outbound windows
631 -void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
632 - u64 pci_addr, u32 type, u64 size)
633 +void __program_ob_windows(struct mobiveil_pcie *pcie, u8 func_no, int win_num,
634 + u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
637 u64 size64 = ~(size - 1);
639 - if (win_num >= pcie->apio_wins) {
640 - dev_err(&pcie->pdev->dev,
641 - "ERROR: max outbound windows reached !\n");
646 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
647 * to 4 KB in PAB_AXI_AMAP_CTRL register
648 @@ -192,6 +186,7 @@ void program_ob_windows(struct mobiveil_
650 csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
652 + csr_writel(pcie, func_no, PAB_AXI_AMAP_PCI_HDR_PARAM(win_num));
654 * program AXI window base with appropriate value in
655 * PAB_AXI_AMAP_AXI_WIN0 register
656 @@ -205,10 +200,98 @@ void program_ob_windows(struct mobiveil_
657 PAB_AXI_AMAP_PEX_WIN_L(win_num));
658 csr_writel(pcie, upper_32_bits(pci_addr),
659 PAB_AXI_AMAP_PEX_WIN_H(win_num));
662 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
663 + u64 pci_addr, u32 type, u64 size)
665 + if (win_num >= pcie->apio_wins) {
666 + dev_err(&pcie->pdev->dev,
667 + "ERROR: max outbound windows reached !\n");
671 + __program_ob_windows(pcie, 0, win_num, cpu_addr,
672 + pci_addr, type, size);
674 pcie->ob_wins_configured++;
677 +void program_ob_windows_ep(struct mobiveil_pcie *pcie, u8 func_no, int win_num,
678 + u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
680 + if (size & (size - 1))
681 + size = 1 << (1 + ilog2(size));
683 + __program_ob_windows(pcie, func_no, win_num, cpu_addr,
684 + pci_addr, type, size);
687 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
690 + csr_writel(pcie, upper_32_bits(phys),
691 + PAB_EXT_PEX_BAR_AMAP(func_no, bar));
692 + csr_writel(pcie, lower_32_bits(phys) | PEX_BAR_AMAP_EN,
693 + PAB_PEX_BAR_AMAP(func_no, bar));
696 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pcie,
697 + u8 func_no, u8 bar)
701 + val = csr_readl(pcie, PAB_PEX_BAR_AMAP(func_no, bar));
703 + csr_writel(pcie, val, PAB_PEX_BAR_AMAP(func_no, bar));
706 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num)
710 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
711 + val &= ~(1 << WIN_ENABLE_SHIFT);
712 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
715 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pcie)
719 + val = csr_readl(pcie, PAB_CTRL);
720 + val |= 1 << AMBA_PIO_ENABLE_SHIFT;
721 + val |= 1 << PEX_PIO_ENABLE_SHIFT;
722 + csr_writel(pcie, val, PAB_CTRL);
725 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pcie)
729 + val = csr_readl(pcie, PAB_AXI_PIO_CTRL);
730 + val |= APIO_EN_MASK;
731 + csr_writel(pcie, val, PAB_AXI_PIO_CTRL);
734 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pcie)
738 + val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
739 + val |= 1 << PIO_ENABLE_SHIFT;
740 + csr_writel(pcie, val, PAB_PEX_PIO_CTRL);
743 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pcie)
747 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
748 + val |= PAB_INTP_PAMR;
749 + csr_writel(pcie, val, PAB_INTP_AMBA_MISC_ENB);
752 int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
755 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
756 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
758 #include <linux/pci.h>
759 #include <linux/irq.h>
760 #include <linux/msi.h>
761 +#include <linux/pci-epc.h>
762 +#include <linux/pci-epf.h>
764 #include "../../pci.h"
766 +#define MAX_IATU_OUT 256
767 /* register offsets and bit positions */
771 #define PAGE_SEL_MASK 0x3f
772 #define PAGE_LO_MASK 0x3ff
773 #define PAGE_SEL_OFFSET_SHIFT 10
774 +#define FUNC_SEL_SHIFT 19
775 +#define FUNC_SEL_MASK 0x1ff
776 +#define MSI_SW_CTRL_EN BIT(29)
778 #define PAB_ACTIVITY_STAT 0x81c
781 #define PIO_ENABLE_SHIFT 0
783 #define PAB_INTP_AMBA_MISC_ENB 0x0b0c
784 +#define PAB_INTP_PAMR BIT(0)
785 #define PAB_INTP_AMBA_MISC_STAT 0x0b1c
786 #define PAB_INTP_RESET BIT(1)
787 #define PAB_INTP_MSI BIT(3)
789 #define WIN_TYPE_MASK 0x3
790 #define WIN_SIZE_MASK 0xfffffc00
792 +#define PAB_AXI_AMAP_PCI_HDR_PARAM(win) PAB_EXT_REG_ADDR(0x5ba0, win)
794 #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
796 #define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
798 #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
799 #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
801 +/* PPIO WINs EP mode */
802 +#define PAB_PEX_BAR_AMAP(func, bar) (0x1ba0 + 0x20 * func + 4 * bar)
803 +#define PAB_EXT_PEX_BAR_AMAP(func, bar) (0x84a0 + 0x20 * func + 4 * bar)
804 +#define PEX_BAR_AMAP_EN BIT(0)
806 +#define PAB_MSIX_TABLE_PBA_ACCESS 0xD000
808 +#define GPEX_BAR_ENABLE 0x4D4
809 +#define GPEX_BAR_SIZE_LDW 0x4D8
810 +#define GPEX_BAR_SIZE_UDW 0x4DC
811 +#define GPEX_BAR_SELECT 0x4E0
813 /* starting offset of INTX bits in status register */
814 #define PAB_INTX_START 5
817 ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
819 struct mobiveil_pcie;
820 +struct mobiveil_pcie_ep;
822 struct mobiveil_msi { /* MSI information */
823 struct mutex lock; /* protect bitmap variable */
824 @@ -170,6 +193,28 @@ struct mobiveil_pab_ops {
825 int (*host_init)(struct mobiveil_pcie *pcie);
828 +struct mobiveil_pcie_ep_ops {
829 + void (*ep_init)(struct mobiveil_pcie_ep *ep);
830 + int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
831 + enum pci_epc_irq_type type, u16 interrupt_num);
832 + const struct pci_epc_features* (*get_features)
833 + (struct mobiveil_pcie_ep *ep);
836 +struct mobiveil_pcie_ep {
837 + struct pci_epc *epc;
838 + const struct mobiveil_pcie_ep_ops *ops;
839 + phys_addr_t phys_base;
842 + phys_addr_t *apio_addr;
843 + unsigned long *apio_wins_map;
845 + void __iomem *msi_mem;
846 + phys_addr_t msi_mem_phys;
850 struct mobiveil_pcie {
851 struct platform_device *pdev;
852 struct list_head *resources;
853 @@ -183,8 +228,12 @@ struct mobiveil_pcie {
854 const struct mobiveil_pab_ops *ops;
856 struct pci_host_bridge *bridge;
857 + struct mobiveil_pcie_ep ep;
860 +#define to_mobiveil_pcie_from_ep(endpoint) \
861 + container_of((endpoint), struct mobiveil_pcie, ep)
863 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
864 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
865 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
866 @@ -226,4 +275,23 @@ static inline void csr_writeb(struct mob
867 csr_write(pcie, val, off, 0x1);
870 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
871 + int bar, u64 phys);
872 +void program_ob_windows_ep(struct mobiveil_pcie *pcie, u8 func_num, int win_num,
873 + u64 cpu_addr, u64 pci_addr, u32 type, u64 size);
874 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
875 + u8 func_no, u8 bar);
876 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num);
877 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
878 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no);
879 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
881 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
882 + u16 interrupt_num);
883 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, u8 bar);
884 +u8 mobiveil_pcie_ep_get_bar_num(struct mobiveil_pcie_ep *ep, u8 func_no);
885 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
886 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
887 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
888 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
889 #endif /* _PCIE_MOBIVEIL_H */