target/linux/layerscape/patches-5.4/812-pcie-0018-PCI-mobiveil-Add-workaround-for-unsupported-request-.patch

   1 From 7cc1ca9e3a87027dbe6598a0c50cb466fc5861e4 Mon Sep 17 00:00:00 2001
   2 From: Xiaowei Bao <xiaowei.bao@nxp.com>
   3 Date: Tue, 22 Jan 2019 19:19:30 +0800
   4 Subject: [PATCH] PCI: mobiveil: Add workaround for unsupported request error
   5
   6 Errata: unsupported request error on inbound posted write
   7 transaction, PCIe controller reports advisory error instead
   8 of uncorrectable error message to RC.
   9
  10 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
  11 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  12 ---
  13  drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +++++++++++++
  14  drivers/pci/controller/mobiveil/pcie-mobiveil.h           |  4 ++++
  15  2 files changed, 17 insertions(+)
  16
  17 --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
  18 +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
  19 @@ -49,6 +49,19 @@ static void ls_pcie_g4_ep_init(struct mo
  20         struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
  21         int win_idx;
  22         u8 bar;
  23 +       u32 val;
  24 +
  25 +       /*
  26 +        * Errata: unsupported request error on inbound posted write
  27 +        * transaction, PCIe controller reports advisory error instead
  28 +        * of uncorrectable error message to RC.
  29 +        * workaround: set the bit20(unsupported_request_Error_severity) with
  30 +        * value 1 in uncorrectable_Error_Severity_Register, make the
  31 +        * unsupported request error generate the fatal error.
  32 +        */
  33 +       val =  csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
  34 +       val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
  35 +       csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
  36
  37         ep->bar_num = PCIE_LX2_BAR_NUM;
  38
  39 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
  40 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
  41 @@ -123,6 +123,10 @@
  42  #define GPEX_BAR_SIZE_UDW              0x4DC
  43  #define GPEX_BAR_SELECT                        0x4E0
  44
  45 +#define CFG_UNCORRECTABLE_ERROR_SEVERITY       0x10c
  46 +#define UNSUPPORTED_REQUEST_ERROR_SHIFT                20
  47 +#define CFG_UNCORRECTABLE_ERROR_MASK           0x108
  48 +
  49  /* starting offset of INTX bits in status register */
  50  #define PAB_INTX_START                 5
  51