2 * Moschip MCS814x clock routines
4 * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/export.h>
11 #include <linux/spinlock.h>
12 #include <linux/err.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk.h>
17 #include <mach/mcs814x.h>
22 #define MHZ (KHZ * KHZ)
25 unsigned long (*get_rate
)(struct clk
*clk
);
26 int (*set_rate
)(struct clk
*clk
, unsigned long rate
);
27 struct clk
*(*get_parent
)(struct clk
*clk
);
28 int (*enable
)(struct clk
*clk
, int enable
);
32 struct clk
*parent
; /* parent clk */
33 unsigned long rate
; /* clock rate in Hz */
34 unsigned long divider
; /* clock divider */
35 u32 usecount
; /* reference count */
36 struct clk_ops
*ops
; /* clock operation */
37 u32 enable_reg
; /* clock enable register */
38 u32 enable_mask
; /* clock enable mask */
41 static unsigned long clk_divide_parent(struct clk
*clk
)
43 if (clk
->parent
&& clk
->divider
)
44 return clk_get_rate(clk
->parent
) / clk
->divider
;
49 static int clk_local_onoff_enable(struct clk
*clk
, int enable
)
53 /* no enable_reg means the clock is always enabled */
57 tmp
= readl_relaxed(mcs814x_sysdbg_base
+ clk
->enable_reg
);
59 tmp
&= ~clk
->enable_mask
;
61 tmp
|= clk
->enable_mask
;
63 writel_relaxed(tmp
, mcs814x_sysdbg_base
+ clk
->enable_reg
);
68 static struct clk_ops default_clk_ops
= {
69 .get_rate
= clk_divide_parent
,
70 .enable
= clk_local_onoff_enable
,
73 static DEFINE_SPINLOCK(clocks_lock
);
75 static const unsigned long cpu_freq_table
[] = {
94 static struct clk clk_cpu
;
96 /* System clock is fixed at 50Mhz */
97 static struct clk clk_sys
= {
101 static struct clk clk_sdram
;
103 static struct clk clk_timer0
= {
104 .parent
= &clk_sdram
,
106 .ops
= &default_clk_ops
,
109 static struct clk clk_timer1_2
= {
113 /* Watchdog clock is system clock / 128 */
114 static struct clk clk_wdt
= {
117 .ops
= &default_clk_ops
,
120 static struct clk clk_emac
= {
121 .ops
= &default_clk_ops
,
122 .enable_reg
= SYSDBG_SYSCTL
,
123 .enable_mask
= SYSCTL_EMAC
,
126 static struct clk clk_ephy
= {
127 .ops
= &default_clk_ops
,
128 .enable_reg
= SYSDBG_PLL_CTL
,
129 .enable_mask
= ~SYSCTL_EPHY
, /* active low */
132 static struct clk clk_cipher
= {
133 .ops
= &default_clk_ops
,
134 .enable_reg
= SYSDBG_SYSCTL
,
135 .enable_mask
= SYSCTL_CIPHER
,
138 #define CLK(_dev, _con, _clk) \
139 { .dev_id = (_dev), .con_id = (_con), .clk = (_clk) },
141 static struct clk_lookup mcs814x_chip_clks
[] = {
142 CLK("cpu", NULL
, &clk_cpu
)
143 CLK("sys", NULL
, &clk_sys
)
144 CLK("sdram", NULL
, &clk_sdram
)
146 CLK("timer0", NULL
, &clk_timer0
)
148 CLK("timer1", NULL
, &clk_timer1_2
)
149 /* 64-bits timer2, same as timer 1 */
150 CLK("timer2", NULL
, &clk_timer1_2
)
151 CLK(NULL
, "wdt", &clk_wdt
)
152 CLK(NULL
, "emac", &clk_emac
)
153 CLK(NULL
, "ephy", &clk_ephy
)
154 CLK(NULL
, "cipher", &clk_cipher
)
157 static void local_clk_disable(struct clk
*clk
)
159 WARN_ON(!clk
->usecount
);
161 if (clk
->usecount
> 0) {
164 if ((clk
->usecount
== 0) && (clk
->ops
->enable
))
165 clk
->ops
->enable(clk
, 0);
168 local_clk_disable(clk
->parent
);
172 static int local_clk_enable(struct clk
*clk
)
177 ret
= local_clk_enable(clk
->parent
);
182 if ((clk
->usecount
== 0) && (clk
->ops
->enable
))
183 ret
= clk
->ops
->enable(clk
, 1);
187 else if (clk
->parent
&& clk
->parent
->ops
->enable
)
188 local_clk_disable(clk
->parent
);
193 int clk_enable(struct clk
*clk
)
198 spin_lock_irqsave(&clocks_lock
, flags
);
199 ret
= local_clk_enable(clk
);
200 spin_unlock_irqrestore(&clocks_lock
, flags
);
204 EXPORT_SYMBOL(clk_enable
);
206 void clk_disable(struct clk
*clk
)
210 spin_lock_irqsave(&clocks_lock
, flags
);
211 local_clk_disable(clk
);
212 spin_unlock_irqrestore(&clocks_lock
, flags
);
214 EXPORT_SYMBOL(clk_disable
);
216 unsigned long clk_get_rate(struct clk
*clk
)
218 if (unlikely(IS_ERR_OR_NULL(clk
)))
224 if (clk
->ops
&& clk
->ops
->get_rate
)
225 return clk
->ops
->get_rate(clk
);
227 return clk_get_rate(clk
->parent
);
229 EXPORT_SYMBOL(clk_get_rate
);
231 struct clk
*clk_get_parent(struct clk
*clk
)
235 if (unlikely(IS_ERR_OR_NULL(clk
)))
238 if (!clk
->ops
|| !clk
->ops
->get_parent
)
241 spin_lock_irqsave(&clocks_lock
, flags
);
242 clk
->parent
= clk
->ops
->get_parent(clk
);
243 spin_unlock_irqrestore(&clocks_lock
, flags
);
247 EXPORT_SYMBOL(clk_get_parent
);
249 void __init
mcs814x_clk_init(void)
254 clkdev_add_table(mcs814x_chip_clks
, ARRAY_SIZE(mcs814x_chip_clks
));
256 /* read the bootstrap registers to know the exact clocking scheme */
257 bs1
= readl_relaxed(mcs814x_sysdbg_base
+ SYSDBG_BS1
);
258 cpu_freq
= (bs1
>> CPU_FREQ_SHIFT
) & CPU_FREQ_MASK
;
260 pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table
[cpu_freq
]);
261 clk_cpu
.rate
= cpu_freq
* KHZ
;
263 /* read SDRAM frequency */
264 if (bs1
& SDRAM_FREQ_BIT
)
265 clk_sdram
.rate
= 100 * MHZ
;
267 clk_sdram
.rate
= 133 * MHZ
;
269 pr_info("SDRAM frequency: %lu (MHz)\n", clk_sdram
.rate
/ MHZ
);