1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/gpio.h>
11 #include "mt7622.dtsi"
12 #include "mt6380.dtsi"
15 model = "Bananapi BPI-R64";
16 compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
23 stdout-path = "serial0:115200n8";
24 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
29 proc-supply = <&mt6380_vcpu_reg>;
30 sram-supply = <&mt6380_vm_reg>;
34 proc-supply = <&mt6380_vcpu_reg>;
35 sram-supply = <&mt6380_vm_reg>;
40 compatible = "gpio-keys";
45 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
50 linux,code = <KEY_WPS_BUTTON>;
51 gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
56 compatible = "gpio-leds";
59 label = "bpi-r64:pio:green";
60 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
64 label = "bpi-r64:pio:red";
65 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
70 reg = <0 0x40000000 0 0x40000000>;
73 reg_1p8v: regulator-1p8v {
74 compatible = "regulator-fixed";
75 regulator-name = "fixed-1.8V";
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <1800000>;
81 reg_3p3v: regulator-3p3v {
82 compatible = "regulator-fixed";
83 regulator-name = "fixed-3.3V";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
90 reg_5v: regulator-5v {
91 compatible = "regulator-fixed";
92 regulator-name = "fixed-5V";
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&irrx_pins>;
117 compatible = "mediatek,eth-mac";
119 phy-mode = "2500base-x";
129 compatible = "mediatek,eth-mac";
141 #address-cells = <1>;
145 compatible = "mediatek,mt7531";
147 reset-gpios = <&pio 54 0>;
150 #address-cells = <1>;
182 phy-mode = "2500base-x";
197 pinctrl-names = "default";
198 pinctrl-0 = <&i2c1_pins>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&i2c2_pins>;
209 pinctrl-names = "default", "state_uhs";
210 pinctrl-0 = <&emmc_pins_default>;
211 pinctrl-1 = <&emmc_pins_uhs>;
214 max-frequency = <50000000>;
217 vmmc-supply = <®_3p3v>;
218 vqmmc-supply = <®_1p8v>;
219 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
220 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
225 pinctrl-names = "default", "state_uhs";
226 pinctrl-0 = <&sd0_pins_default>;
227 pinctrl-1 = <&sd0_pins_uhs>;
230 max-frequency = <50000000>;
233 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
234 vmmc-supply = <®_3p3v>;
235 vqmmc-supply = <®_3p3v>;
236 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
237 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
241 pinctrl-names = "default";
242 pinctrl-0 = <¶llel_nand_pins>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&spi_nor_pins>;
252 compatible = "jedec,spi-nor";
258 pinctrl-names = "default";
259 pinctrl-0 = <&pcie0_pins>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pcie1_pins>;
270 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
271 * SATA functions. i.e. output-high: PCIe, output-low: SATA
275 gpios = <90 GPIO_ACTIVE_HIGH>;
279 /* eMMC is shared pin with parallel NAND */
280 emmc_pins_default: emmc-pins-default {
282 function = "emmc", "emmc_rst";
286 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
287 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
288 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
291 pins = "NDL0", "NDL1", "NDL2",
292 "NDL3", "NDL4", "NDL5",
293 "NDL6", "NDL7", "NRB";
304 emmc_pins_uhs: emmc-pins-uhs {
311 pins = "NDL0", "NDL1", "NDL2",
312 "NDL3", "NDL4", "NDL5",
313 "NDL6", "NDL7", "NRB";
315 drive-strength = <4>;
321 drive-strength = <4>;
329 groups = "mdc_mdio", "rgmii_via_gmac2";
333 i2c1_pins: i2c1-pins {
340 i2c2_pins: i2c2-pins {
347 i2s1_pins: i2s1-pins {
350 groups = "i2s_out_mclk_bclk_ws",
356 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
357 "I2S_WS", "I2S_MCLK";
358 drive-strength = <12>;
363 irrx_pins: irrx-pins {
370 irtx_pins: irtx-pins {
377 /* Parallel nand is shared pin with eMMC */
378 parallel_nand_pins: parallel-nand-pins {
385 pcie0_pins: pcie0-pins {
388 groups = "pcie0_pad_perst",
394 pcie1_pins: pcie1-pins {
397 groups = "pcie1_pad_perst",
403 pmic_bus_pins: pmic-bus-pins {
410 pwm7_pins: pwm1-2-pins {
413 groups = "pwm_ch7_2";
417 wled_pins: wled-pins {
424 sd0_pins_default: sd0-pins-default {
430 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
431 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
432 * DAT2, DAT3, CMD, CLK for SD respectively.
435 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
436 "I2S2_IN","I2S4_OUT";
438 drive-strength = <8>;
443 drive-strength = <12>;
452 sd0_pins_uhs: sd0-pins-uhs {
459 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
460 "I2S2_IN","I2S4_OUT";
471 /* Serial NAND is shared pin with SPI-NOR */
472 serial_nand_pins: serial-nand-pins {
479 spic0_pins: spic0-pins {
486 spic1_pins: spic1-pins {
493 /* SPI-NOR is shared pin with serial NAND */
494 spi_nor_pins: spi-nor-pins {
501 /* serial NAND is shared pin with SPI-NOR */
502 serial_nand_pins: serial-nand-pins {
509 uart0_pins: uart0-pins {
512 groups = "uart0_0_tx_rx" ;
516 uart2_pins: uart2-pins {
519 groups = "uart2_1_tx_rx" ;
523 watchdog_pins: watchdog-pins {
525 function = "watchdog";
532 pinctrl-names = "default";
533 pinctrl-0 = <&pwm7_pins>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pmic_bus_pins>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&spic0_pins>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&spic1_pins>;
565 vusb33-supply = <®_3p3v>;
566 vbus-supply = <®_5v>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&uart0_pins>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&uart2_pins>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&watchdog_pins>;