1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
10 model = "D-Link EAGLE PRO AI M32 A1";
11 compatible = "dlink,eagle-pro-ai-m32-a1", "mediatek,mt7622";
14 led-boot = &status_orange;
15 led-failsafe = &status_red;
16 led-running = &status_white;
17 led-upgrade = &status_red;
19 label-mac-device = &gmac0;
23 stdout-path = "serial0:115200n8";
24 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
29 proc-supply = <&mt6380_vcpu_reg>;
30 sram-supply = <&mt6380_vm_reg>;
34 proc-supply = <&mt6380_vcpu_reg>;
35 sram-supply = <&mt6380_vm_reg>;
40 compatible = "gpio-keys";
43 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
45 linux,code = <KEY_RESTART>;
49 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
51 linux,code = <KEY_WPS_BUTTON>;
56 compatible = "gpio-leds";
58 status_white: status_white {
59 label = "white:status";
60 gpios = <&pio 85 GPIO_ACTIVE_LOW>;
63 status_orange: status_orange {
64 label = "orange:status";
65 gpios = <&pio 20 GPIO_ACTIVE_LOW>;
69 status_red: status_red {
71 gpios = <&pio 17 GPIO_ACTIVE_LOW>;
76 reg = <0 0x40000000 0 0x40000000>;
89 pinctrl-names = "default";
90 pinctrl-0 = <ð_pins>;
94 compatible = "mediatek,eth-mac";
95 nvmem-cells = <&macaddr_odm_83>;
96 nvmem-cell-names = "mac-address";
97 phy-mode = "2500base-x";
108 #address-cells = <1>;
112 compatible = "mediatek,mt7531";
114 interrupt-controller;
115 #interrupt-cells = <1>;
116 interrupt-parent = <&pio>;
117 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
118 reset-gpios = <&pio 54 0>;
121 #address-cells = <1>;
142 phy-mode = "2500base-x";
156 pinctrl-names = "default";
157 pinctrl-0 = <&pcie0_pins>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pcie1_pins>;
168 epa_elna_pins: epa-elna-pins {
171 groups = "antsel0", "antsel1", "antsel2", "antsel3",
172 "antsel4", "antsel5", "antsel6", "antsel7",
173 "antsel8", "antsel9", "antsel12", "antsel13",
174 "antsel14", "antsel15", "antsel16", "antsel17";
181 groups = "mdc_mdio", "rgmii_via_gmac2";
185 pcie0_pins: pcie0-pins {
188 groups = "pcie0_pad_perst",
194 pcie1_pins: pcie1-pins {
197 groups = "pcie1_pad_perst",
203 pmic_bus_pins: pmic-bus-pins {
210 /* Serial NAND is shared pin with SPI-NOR */
211 serial_nand_pins: serial-nand-pins {
218 uart0_pins: uart0-pins {
221 groups = "uart0_0_tx_rx";
225 watchdog_pins: watchdog-pins {
227 function = "watchdog";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pmic_bus_pins>;
253 reg = <0x0000 0 0 0 0>;
254 ieee80211-freq-limit = <5000000 6000000>;
255 mediatek,mtd-eeprom = <&factory 0x05000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&serial_nand_pins>;
265 compatible = "spi-nand";
266 mediatek,bmt-table-size = <0x1000>;
268 nand-ecc-engine = <&snfi>;
270 spi-rx-bus-width = <4>;
271 spi-tx-bus-width = <4>;
274 compatible = "fixed-partitions";
275 #address-cells = <1>;
280 reg = <0x00000000 0x00080000>;
286 reg = <0x00080000 0x00040000>;
291 label = "Bootloader";
292 reg = <0x000C0000 0x00080000>;
297 label = "BootConfig";
298 reg = <0x00140000 0x00040000>;
302 odm: partition@180000 {
304 reg = <0x00180000 0x00040000>;
308 compatible = "fixed-layout";
309 #address-cells = <1>;
312 macaddr_odm_83: macaddr@83 {
318 config1: partition@1C0000 {
320 reg = <0x001C0000 0x00080000>;
326 reg = <0x00240000 0x00080000>;
332 reg = <0x002C0000 0x02D00000>;
334 compatible = "fixed-partitions";
335 #address-cells = <1>;
339 reg = <0x00000000 0x00800000>;
344 reg = <0x00800000 0x02500000>;
350 reg = <0x02FC0000 0x02D00000>;
354 factory: partition@5CC0000 {
356 reg = <0x05CC0000 0x00100000>;
362 reg = <0x05DC0000 0x00200000>;
368 reg = <0x05FC0000 0x00300000>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&uart0_pins>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&watchdog_pins>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&epa_elna_pins>;
398 mediatek,mtd-eeprom = <&factory 0x0000>;