1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
12 model = "ELECOM WRC-X3200GST3";
13 compatible = "elecom,wrc-x3200gst3", "mediatek,mt7622";
17 led-boot = &led_power_green;
18 led-failsafe = &led_power_red;
19 led-running = &led_power_green;
20 led-upgrade = &led_power_green;
21 label-mac-device = &wan;
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
29 reg = <0 0x40000000 0 0x1f000000>;
33 compatible = "gpio-leds";
37 gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
38 color = <LED_COLOR_ID_RED>;
39 function = LED_FUNCTION_WPS;
42 led_power_red: led-1 {
44 gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
45 color = <LED_COLOR_ID_RED>;
46 function = LED_FUNCTION_POWER;
47 function-enumerator = <1>;
50 led_power_green: led-2 {
51 label = "green:power";
52 gpios = <&pio 49 GPIO_ACTIVE_HIGH>;
53 color = <LED_COLOR_ID_GREEN>;
54 function = LED_FUNCTION_POWER;
55 function-enumerator = <2>;
60 gpios = <&pio 50 GPIO_ACTIVE_HIGH>;
61 color = <LED_COLOR_ID_BLUE>;
62 function = LED_FUNCTION_POWER;
63 function-enumerator = <3>;
67 label = "white:wlan2g";
68 gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
69 color = <LED_COLOR_ID_WHITE>;
70 function = LED_FUNCTION_WLAN;
71 function-enumerator = <1>;
72 linux,default-trigger = "phy0tpt";
76 label = "white:wlan5g";
77 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
78 color = <LED_COLOR_ID_WHITE>;
79 function = LED_FUNCTION_WLAN;
80 function-enumerator = <2>;
81 linux,default-trigger = "phy1radio";
86 compatible = "gpio-keys";
90 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
91 linux,code = <KEY_RESTART>;
96 gpios = <&pio 42 GPIO_ACTIVE_LOW>;
98 linux,input-type = <EV_SW>;
103 gpios = <&pio 43 GPIO_ACTIVE_LOW>;
104 linux,code = <BTN_1>;
105 linux,input-type = <EV_SW>;
110 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
111 linux,code = <KEY_WPS_BUTTON>;
117 proc-supply = <&mt6380_vcpu_reg>;
118 sram-supply = <&mt6380_vm_reg>;
122 proc-supply = <&mt6380_vcpu_reg>;
123 sram-supply = <&mt6380_vm_reg>;
130 groups = "mdc_mdio", "rgmii_via_gmac2";
134 pcie0_pins: pcie0-pins {
137 groups = "pcie0_pad_perst",
143 pmic_bus_pins: pmic-bus-pins {
150 pwm7_pins: pwm1-2-pins {
153 groups = "pwm_ch7_2";
157 /* Serial NAND is shared pin with SPI-NOR */
158 serial_nand_pins: serial-nand-pins {
165 pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI",
166 "SPI_MISO", "SPI_CS";
167 drive-strength = <16>;
173 drive-strength = <16>;
178 uart0_pins: uart0-pins {
181 groups = "uart0_0_tx_rx" ;
185 watchdog_pins: watchdog-pins {
187 function = "watchdog";
194 pinctrl-names = "default";
195 pinctrl-0 = <ð_pins>;
199 compatible = "mediatek,eth-mac";
202 phy-connection-type = "2500base-x";
204 nvmem-cells = <&macaddr_factory_7fff4>;
205 nvmem-cell-names = "mac-address";
215 #address-cells = <1>;
219 compatible = "mediatek,mt7531";
221 interrupt-controller;
222 #interrupt-cells = <1>;
223 interrupt-parent = <&pio>;
224 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
225 reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
228 #address-cells = <1>;
235 nvmem-cells = <&macaddr_factory_7fffa>;
236 nvmem-cell-names = "mac-address";
262 phy-mode = "2500base-x";
280 pinctrl-names = "default";
281 pinctrl-0 = <&serial_nand_pins>;
285 compatible = "spi-nand";
287 spi-tx-bus-width = <4>;
288 spi-rx-bus-width = <4>;
289 nand-ecc-engine = <&snfi>;
291 mediatek,bmt-table-size = <0x1000>;
292 mediatek,bmt-remap-range = <0x0 0x8c0000>,
293 <0x1bc0000 0x30c0000>;
296 compatible = "fixed-partitions";
297 #address-cells = <1>;
308 reg = <0x80000 0x40000>;
314 reg = <0xc0000 0x80000>;
319 label = "u-boot-env";
320 reg = <0x140000 0x80000>;
324 factory: partition@1c0000 {
326 reg = <0x1c0000 0x100000>;
329 compatible = "nvmem-cells";
330 #address-cells = <1>;
333 macaddr_factory_4: macaddr@4 {
337 macaddr_factory_7fff4: macaddr@7fff4 {
341 macaddr_factory_7fffa: macaddr@7fffa {
348 reg = <0x2c0000 0x600000>;
353 reg = <0x8c0000 0x1300000>;
357 label = "tm_pattern";
358 reg = <0x1bc0000 0x500000>;
364 reg = <0x20c0000 0x100000>;
370 reg = <0x21c0000 0xf00000>;
376 reg = <0x30c0000 0x4f40000>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pcie0_pins>;
393 compatible = "mediatek,mt76";
394 reg = <0x0000 0 0 0 0>;
395 mediatek,mtd-eeprom = <&factory 0x5000>;
396 ieee80211-freq-limit = <5000000 6000000>;
397 nvmem-cells = <&macaddr_factory_4>;
398 nvmem-cell-names = "mac-address";
399 mac-address-increment = <1>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pwm7_pins>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pmic_bus_pins>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart0_pins>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&watchdog_pins>;
434 mediatek,mtd-eeprom = <&factory 0x0>;