mediatek: disable btif for mt7622 devices
[openwrt/staging/981213.git] / target / linux / mediatek / dts / mt7622-linksys-e8450.dtsi
1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6
7 #include "mt7622.dtsi"
8 #include "mt6380.dtsi"
9
10 / {
11 compatible = "linksys,e8450", "mediatek,mt7622";
12
13 aliases {
14 serial0 = &uart0;
15 led-boot = &led_power;
16 led-failsafe = &led_power;
17 led-running = &led_power;
18 led-upgrade = &led_power;
19 };
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
24 };
25
26 cpus {
27 cpu@0 {
28 proc-supply = <&mt6380_vcpu_reg>;
29 sram-supply = <&mt6380_vm_reg>;
30 };
31
32 cpu@1 {
33 proc-supply = <&mt6380_vcpu_reg>;
34 sram-supply = <&mt6380_vm_reg>;
35 };
36 };
37
38 gpio-keys {
39 compatible = "gpio-keys";
40
41 factory {
42 label = "reset";
43 linux,code = <KEY_RESTART>;
44 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
45 };
46
47 wps {
48 label = "wps";
49 linux,code = <KEY_WPS_BUTTON>;
50 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
51 };
52 };
53
54 gpio-leds {
55 compatible = "gpio-leds";
56
57 led_power: power_blue {
58 label = "power:blue";
59 gpios = <&pio 95 GPIO_ACTIVE_LOW>;
60 default-state = "on";
61 };
62
63 power_orange {
64 label = "power:orange";
65 gpios = <&pio 96 GPIO_ACTIVE_LOW>;
66 default-state = "off";
67 };
68
69 inet_blue {
70 label = "inet:blue";
71 gpios = <&pio 97 GPIO_ACTIVE_LOW>;
72 default-state = "off";
73 };
74
75 inet_orange {
76 label = "inet:orange";
77 gpios = <&pio 98 GPIO_ACTIVE_LOW>;
78 default-state = "off";
79 };
80 };
81
82 memory {
83 reg = <0 0x40000000 0 0x40000000>;
84 };
85
86 reg_1p8v: regulator-1p8v {
87 compatible = "regulator-fixed";
88 regulator-name = "fixed-1.8V";
89 regulator-min-microvolt = <1800000>;
90 regulator-max-microvolt = <1800000>;
91 regulator-always-on;
92 };
93
94 reg_3p3v: regulator-3p3v {
95 compatible = "regulator-fixed";
96 regulator-name = "fixed-3.3V";
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 regulator-boot-on;
100 regulator-always-on;
101 };
102
103 reg_5v: regulator-5v {
104 compatible = "regulator-fixed";
105 regulator-name = "fixed-5V";
106 regulator-min-microvolt = <5000000>;
107 regulator-max-microvolt = <5000000>;
108 regulator-boot-on;
109 regulator-always-on;
110 };
111 };
112
113 &cir {
114 pinctrl-names = "default";
115 pinctrl-0 = <&irrx_pins>;
116 status = "okay";
117 };
118
119 &eth {
120 pinctrl-names = "default";
121 pinctrl-0 = <&eth_pins>;
122 status = "okay";
123
124 gmac0: mac@0 {
125 compatible = "mediatek,eth-mac";
126 reg = <0>;
127 phy-mode = "2500base-x";
128
129 fixed-link {
130 speed = <2500>;
131 full-duplex;
132 pause;
133 };
134 };
135
136 mdio-bus {
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 switch@0 {
141 compatible = "mediatek,mt7531";
142 reg = <0>;
143 interrupt-controller;
144 #interrupt-cells = <1>;
145 interrupt-parent = <&pio>;
146 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
147 reset-gpios = <&pio 54 0>;
148
149 ports {
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 port@0 {
154 reg = <0>;
155 label = "lan1";
156 };
157
158 port@1 {
159 reg = <1>;
160 label = "lan2";
161 };
162
163 port@2 {
164 reg = <2>;
165 label = "lan3";
166 };
167
168 port@3 {
169 reg = <3>;
170 label = "lan4";
171 };
172
173 wan: port@4 {
174 reg = <4>;
175 label = "wan";
176 };
177
178 port@6 {
179 reg = <6>;
180 ethernet = <&gmac0>;
181 phy-mode = "2500base-x";
182
183 fixed-link {
184 speed = <2500>;
185 full-duplex;
186 pause;
187 };
188 };
189 };
190 };
191
192 };
193 };
194
195 &pcie0 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pcie0_pins>;
198 status = "okay";
199 };
200
201 &pcie1 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pcie1_pins>;
204 status = "okay";
205 };
206
207 &pio {
208 eth_pins: eth-pins {
209 mux {
210 function = "eth";
211 groups = "mdc_mdio", "rgmii_via_gmac2";
212 };
213 };
214
215 irrx_pins: irrx-pins {
216 mux {
217 function = "ir";
218 groups = "ir_1_rx";
219 };
220 };
221
222 irtx_pins: irtx-pins {
223 mux {
224 function = "ir";
225 groups = "ir_1_tx";
226 };
227 };
228
229 pcie0_pins: pcie0-pins {
230 mux {
231 function = "pcie";
232 groups = "pcie0_pad_perst",
233 "pcie0_1_waken",
234 "pcie0_1_clkreq";
235 };
236 };
237
238 pcie1_pins: pcie1-pins {
239 mux {
240 function = "pcie";
241 groups = "pcie1_pad_perst",
242 "pcie1_0_waken",
243 "pcie1_0_clkreq";
244 };
245 };
246
247 pmic_bus_pins: pmic-bus-pins {
248 mux {
249 function = "pmic";
250 groups = "pmic_bus";
251 };
252 };
253
254 pwm7_pins: pwm1-2-pins {
255 mux {
256 function = "pwm";
257 groups = "pwm_ch7_2";
258 };
259 };
260
261 wled_pins: wled-pins {
262 mux {
263 function = "led";
264 groups = "wled";
265 };
266 };
267
268 /* Serial NAND is shared pin with SPI-NOR */
269 serial_nand_pins: serial-nand-pins {
270 mux {
271 function = "flash";
272 groups = "snfi";
273 };
274 };
275
276 spic0_pins: spic0-pins {
277 mux {
278 function = "spi";
279 groups = "spic0_0";
280 };
281 };
282
283 spic1_pins: spic1-pins {
284 mux {
285 function = "spi";
286 groups = "spic1_0";
287 };
288 };
289
290 uart0_pins: uart0-pins {
291 mux {
292 function = "uart";
293 groups = "uart0_0_tx_rx" ;
294 };
295 };
296
297 uart2_pins: uart2-pins {
298 mux {
299 function = "uart";
300 groups = "uart2_1_tx_rx" ;
301 };
302 };
303
304 watchdog_pins: watchdog-pins {
305 mux {
306 function = "watchdog";
307 groups = "watchdog";
308 };
309 };
310 };
311
312 &pwm {
313 pinctrl-names = "default";
314 pinctrl-0 = <&pwm7_pins>;
315 status = "okay";
316 };
317
318 &pwrap {
319 pinctrl-names = "default";
320 pinctrl-0 = <&pmic_bus_pins>;
321
322 status = "okay";
323 };
324
325 &sata {
326 status = "disabled";
327 };
328
329 &sata_phy {
330 status = "disabled";
331 };
332
333 &slot0 {
334 wmac1: wifi@0,0 {
335 compatible = "mediatek,mt76";
336 reg = <0x0000 0 0 0 0>;
337 ieee80211-freq-limit = <5000000 6000000>;
338 mediatek,disable-radar-background;
339 };
340 };
341
342 &bch {
343 status = "okay";
344 };
345
346 &snfi {
347 pinctrl-names = "default";
348 pinctrl-0 = <&serial_nand_pins>;
349 status = "okay";
350
351 snand: flash@0 {
352 compatible = "spi-nand";
353 reg = <0>;
354 spi-tx-bus-width = <4>;
355 spi-rx-bus-width = <4>;
356 nand-ecc-engine = <&snfi>;
357 };
358 };
359
360 &spi0 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&spic0_pins>;
363 status = "okay";
364 };
365
366 &spi1 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&spic1_pins>;
369 status = "okay";
370 };
371
372 &ssusb {
373 vusb33-supply = <&reg_3p3v>;
374 vbus-supply = <&reg_5v>;
375 status = "okay";
376 };
377
378 &u3phy {
379 status = "okay";
380 };
381
382 &uart0 {
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_pins>;
385 status = "okay";
386 };
387
388 &uart2 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&uart2_pins>;
391 status = "okay";
392 };
393
394 &rtc {
395 status = "disabled";
396 };
397
398 &watchdog {
399 pinctrl-names = "default";
400 pinctrl-0 = <&watchdog_pins>;
401 status = "okay";
402 };