1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
11 compatible = "linksys,e8450", "mediatek,mt7622";
15 led-boot = &led_power;
16 led-failsafe = &led_power;
17 led-running = &led_power;
18 led-upgrade = &led_power;
22 stdout-path = "serial0:115200n8";
23 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
28 proc-supply = <&mt6380_vcpu_reg>;
29 sram-supply = <&mt6380_vm_reg>;
33 proc-supply = <&mt6380_vcpu_reg>;
34 sram-supply = <&mt6380_vm_reg>;
39 compatible = "gpio-keys";
43 linux,code = <KEY_RESTART>;
44 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
49 linux,code = <KEY_WPS_BUTTON>;
50 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
55 compatible = "gpio-leds";
57 led_power: power_blue {
59 gpios = <&pio 95 GPIO_ACTIVE_LOW>;
64 label = "power:orange";
65 gpios = <&pio 96 GPIO_ACTIVE_LOW>;
66 default-state = "off";
71 gpios = <&pio 97 GPIO_ACTIVE_LOW>;
72 default-state = "off";
76 label = "inet:orange";
77 gpios = <&pio 98 GPIO_ACTIVE_LOW>;
78 default-state = "off";
83 reg = <0 0x40000000 0 0x40000000>;
86 reg_1p8v: regulator-1p8v {
87 compatible = "regulator-fixed";
88 regulator-name = "fixed-1.8V";
89 regulator-min-microvolt = <1800000>;
90 regulator-max-microvolt = <1800000>;
94 reg_3p3v: regulator-3p3v {
95 compatible = "regulator-fixed";
96 regulator-name = "fixed-3.3V";
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
103 reg_5v: regulator-5v {
104 compatible = "regulator-fixed";
105 regulator-name = "fixed-5V";
106 regulator-min-microvolt = <5000000>;
107 regulator-max-microvolt = <5000000>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&irrx_pins>;
120 pinctrl-names = "default";
121 pinctrl-0 = <ð_pins>;
125 compatible = "mediatek,eth-mac";
127 phy-mode = "2500base-x";
137 #address-cells = <1>;
141 compatible = "mediatek,mt7531";
143 interrupt-controller;
144 #interrupt-cells = <1>;
145 interrupt-parent = <&pio>;
146 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
147 reset-gpios = <&pio 54 0>;
150 #address-cells = <1>;
181 phy-mode = "2500base-x";
196 pinctrl-names = "default";
197 pinctrl-0 = <&pcie0_pins>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pcie1_pins>;
211 groups = "mdc_mdio", "rgmii_via_gmac2";
215 irrx_pins: irrx-pins {
222 irtx_pins: irtx-pins {
229 pcie0_pins: pcie0-pins {
232 groups = "pcie0_pad_perst",
238 pcie1_pins: pcie1-pins {
241 groups = "pcie1_pad_perst",
247 pmic_bus_pins: pmic-bus-pins {
254 pwm7_pins: pwm1-2-pins {
257 groups = "pwm_ch7_2";
261 wled_pins: wled-pins {
268 /* Serial NAND is shared pin with SPI-NOR */
269 serial_nand_pins: serial-nand-pins {
276 spic0_pins: spic0-pins {
283 spic1_pins: spic1-pins {
290 uart0_pins: uart0-pins {
293 groups = "uart0_0_tx_rx" ;
297 uart2_pins: uart2-pins {
300 groups = "uart2_1_tx_rx" ;
304 watchdog_pins: watchdog-pins {
306 function = "watchdog";
313 pinctrl-names = "default";
314 pinctrl-0 = <&pwm7_pins>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pmic_bus_pins>;
335 compatible = "mediatek,mt76";
336 reg = <0x0000 0 0 0 0>;
337 ieee80211-freq-limit = <5000000 6000000>;
338 mediatek,disable-radar-background;
347 pinctrl-names = "default";
348 pinctrl-0 = <&serial_nand_pins>;
352 compatible = "spi-nand";
354 spi-tx-bus-width = <4>;
355 spi-rx-bus-width = <4>;
356 nand-ecc-engine = <&snfi>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&spic0_pins>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&spic1_pins>;
373 vusb33-supply = <®_3p3v>;
374 vbus-supply = <®_5v>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_pins>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&uart2_pins>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&watchdog_pins>;