1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* Copyright (c) 2022, Marcel Ziswiler <marcel@ziswiler.com> */
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
11 model = "Netgear WAX206";
12 compatible = "netgear,wax206", "mediatek,mt7622";
16 led-boot = &led_power_r;
17 led-failsafe = &led_power_r;
18 led-running = &led_power_g;
19 led-upgrade = &led_power_g;
24 stdout-path = "serial0:115200n8";
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
36 sram-supply = <&mt6380_vm_reg>;
41 compatible = "gpio-keys";
44 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
46 linux,code = <KEY_RESTART>;
50 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
52 linux,code = <KEY_WPS_BUTTON>;
57 compatible = "gpio-leds";
59 led_power_r: power_red {
61 gpios = <&pio 3 GPIO_ACTIVE_LOW>;
65 led_power_g: power_green {
66 default-state = "off";
67 gpios = <&pio 4 GPIO_ACTIVE_LOW>;
68 label = "power:green";
72 default-state = "off";
73 gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
78 default-state = "off";
79 gpios = <&pio 17 GPIO_ACTIVE_LOW>;
84 default-state = "off";
85 gpios = <&pio 85 GPIO_ACTIVE_LOW>;
86 label = "wifin:green";
90 default-state = "off";
91 gpios = <&pio 86 GPIO_ACTIVE_LOW>;
96 default-state = "off";
97 gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
98 label = "wifia:green";
102 default-state = "off";
103 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
104 label = "wifia:blue";
109 reg = <0 0x40000000 0 0x40000000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&irrx_pins>;
128 pinctrl-names = "default";
129 pinctrl-0 = <ð_pins>;
133 compatible = "mediatek,eth-mac";
134 nvmem-cells = <&macaddr_factory_7fff4>;
135 nvmem-cell-names = "mac-address";
136 phy-mode = "2500base-x";
147 #address-cells = <1>;
151 compatible = "mediatek,mt7531";
152 #interrupt-cells = <1>;
153 interrupt-controller;
154 interrupt-parent = <&pio>;
155 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
157 reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
160 #address-cells = <1>;
185 nvmem-cells = <&macaddr_factory_7fffa>;
186 nvmem-cell-names = "mac-address";
187 phy-handle = <&rtl8221b_phy>;
188 phy-mode = "2500base-x";
194 phy-mode = "2500base-x";
206 rtl8221b_phy: ethernet-phy@7 {
207 compatible = "ethernet-phy-ieee802.3-c45";
209 reset-gpios = <&pio 101 GPIO_ACTIVE_LOW>;
210 interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
211 reset-assert-us = <100000>;
212 reset-deassert-us = <100000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pcie0_pins>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pcie1_pins>;
233 groups = "mdc_mdio", "rgmii_via_gmac2";
237 irrx_pins: irrx-pins {
244 irtx_pins: irtx-pins {
251 pcie0_pins: pcie0-pins {
254 groups = "pcie0_pad_perst",
260 pcie1_pins: pcie1-pins {
263 groups = "pcie1_pad_perst",
269 pmic_bus_pins: pmic-bus-pins {
276 pwm7_pins: pwm1-2-pins {
279 groups = "pwm_ch7_2";
283 wled_pins: wled-pins {
290 /* Serial NAND is shared pin with SPI-NOR */
291 serial_nand_pins: serial-nand-pins {
298 spic0_pins: spic0-pins {
305 spic1_pins: spic1-pins {
312 uart0_pins: uart0-pins {
315 groups = "uart0_0_tx_rx";
319 uart2_pins: uart2-pins {
322 groups = "uart2_1_tx_rx";
326 watchdog_pins: watchdog-pins {
328 function = "watchdog";
335 pinctrl-names = "default";
336 pinctrl-0 = <&pwm7_pins>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pmic_bus_pins>;
360 reg = <0x0000 0 0 0 0>;
361 ieee80211-freq-limit = <5000000 6000000>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&serial_nand_pins>;
371 compatible = "spi-nand";
372 mediatek,bmt-table-size = <0x1000>;
374 nand-ecc-engine = <&snfi>;
376 spi-rx-bus-width = <4>;
377 spi-tx-bus-width = <4>;
380 compatible = "fixed-partitions";
381 #address-cells = <1>;
386 reg = <0x00000 0x0080000>;
392 reg = <0x80000 0x0040000>;
397 label = "Bootloader";
398 reg = <0xc0000 0x0080000>;
404 reg = <0x140000 0x0080000>;
407 factory: partition@1c0000 {
409 reg = <0x1c0000 0x0100000>;
413 compatible = "fixed-layout";
414 #address-cells = <1>;
417 macaddr_factory_7fff4: macaddr@7fff4 {
421 macaddr_factory_7fffa: macaddr@7fffa {
429 reg = <0x2c0000 0x2600000>;
431 compatible = "fixed-partitions";
432 #address-cells = <1>;
437 reg = <0x0 0x600000>;
442 reg = <0x600000 0x2000000>;
447 label = "firmware_backup";
448 reg = <0x28c0000 0x2600000>;
454 reg = <0x4ec0000 0x800000>;
460 reg = <0x56c0000 0x400000>;
466 reg = <0x5ac0000 0x100000>;
472 reg = <0x5bc0000 0x400000>;
478 reg = <0x5fc0000 0x200000>;
484 reg = <0x61c0000 0x100000>;
489 label = "NTGRcryptK";
490 reg = <0x62c0000 0x100000>;
495 label = "NTGRcryptD";
496 reg = <0x63c0000 0x500000>;
502 reg = <0x68c0000 0x100000>;
508 reg = <0x69c0000 0x640000>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&spic0_pins>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&spic1_pins>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&uart0_pins>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&uart2_pins>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&watchdog_pins>;
555 mediatek,mtd-eeprom = <&factory 0x0000>;
560 mediatek,mtd-eeprom = <&factory 0x05000>;