1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/gpio/gpio.h>
12 model = "TOTOLINK A8000RU";
13 compatible = "totolink,a8000ru", "mediatek,mt7622";
16 label-mac-device = &gmac0;
17 led-boot = &led_status;
18 led-failsafe = &led_status;
19 led-running = &led_status;
20 led-upgrade = &led_status;
25 stdout-path = "serial0:115200n8";
26 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
42 compatible = "gpio-keys";
46 linux,code = <KEY_RESTART>;
47 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
52 linux,code = <KEY_WPS_BUTTON>;
53 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
58 compatible = "gpio-leds";
60 led_status: status_red {
61 function = LED_FUNCTION_STATUS;
62 color = <LED_COLOR_ID_RED>;
63 gpios = <&pio 81 GPIO_ACTIVE_LOW>;
68 reg_1p8v: regulator-1p8v {
69 compatible = "regulator-fixed";
70 regulator-name = "fixed-1.8V";
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
76 reg_3p3v: regulator-3p3v {
77 compatible = "regulator-fixed";
78 regulator-name = "fixed-3.3V";
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
85 reg_5v: regulator-5v {
86 compatible = "regulator-fixed";
87 regulator-name = "fixed-5V";
88 regulator-min-microvolt = <5000000>;
89 regulator-max-microvolt = <5000000>;
95 compatible = "mediatek,rtk-gsw";
96 mediatek,ethsys = <ðsys>;
97 mediatek,mdio = <&mdio>;
98 mediatek,reset-pin = <&pio 54 0>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pcie0_pins>;
111 reg = <0x0000 0 0 0 0>;
112 mediatek,mtd-eeprom = <&factory 0x5000>;
113 ieee80211-freq-limit = <5490000 6000000>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pcie1_pins>;
125 reg = <0x0000 0 0 0 0>;
126 mediatek,mtd-eeprom = <&factory 0x10000>;
127 ieee80211-freq-limit = <5000000 5490000>;
135 groups = "mdc_mdio", "rgmii_via_gmac2";
139 pcie0_pins: pcie0-pins {
142 groups = "pcie0_pad_perst",
148 pcie1_pins: pcie1-pins {
151 groups = "pcie1_pad_perst",
157 pmic_bus_pins: pmic-bus-pins {
164 /* serial NAND is shared pin with SPI-NOR */
165 serial_nand_pins: serial-nand-pins {
172 uart0_pins: uart0-pins {
175 groups = "uart0_0_tx_rx" ;
179 watchdog_pins: watchdog-pins {
181 function = "watchdog";
186 epa_elna_pins: epa-elna-pins {
189 groups = "antsel0", "antsel1", "antsel2", "antsel3",
190 "antsel4", "antsel5", "antsel6", "antsel7",
191 "antsel8", "antsel9", "antsel12", "antsel13",
192 "antsel14", "antsel15", "antsel16", "antsel17";
199 pinctrl-names = "default";
200 pinctrl-0 = <ð_pins>;
203 compatible = "mediatek,eth-mac";
205 nvmem-cells = <&macaddr_factory_2a>;
206 nvmem-cell-names = "mac-address";
207 phy-connection-type = "2500base-x";
216 compatible = "mediatek,eth-mac";
219 nvmem-cells = <&macaddr_factory_24>;
220 nvmem-cell-names = "mac-address";
229 #address-cells = <1>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pmic_bus_pins>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&serial_nand_pins>;
249 compatible = "spi-nand";
251 spi-tx-bus-width = <4>;
252 spi-rx-bus-width = <4>;
253 nand-ecc-engine = <&snfi>;
257 compatible = "fixed-partitions";
258 #address-cells = <1>;
269 reg = <0x80000 0x40000>;
275 reg = <0xc0000 0x80000>;
280 label = "u-boot-env";
281 reg = <0x140000 0x80000>;
285 factory: partition@1c0000 {
287 reg = <0x1c0000 0x40000>;
291 compatible = "fixed-layout";
292 #address-cells = <1>;
295 macaddr_factory_24: macaddr@24 {
299 macaddr_factory_2a: macaddr@2a {
307 reg = <0x200000 0x6400000>;
312 reg = <0x6600000 0x100000>;
315 /* size of this partition varies due to BMT & bad blocks. */
325 vusb33-supply = <®_3p3v>;
326 vbus-supply = <®_5v>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&uart0_pins>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&watchdog_pins>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&epa_elna_pins>;
349 mediatek,mtd-eeprom = <&factory 0x0>;