target/linux/mediatek/dts/mt7622-tplink_tl-xdr3230-v1.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/leds/common.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 #include "mt7622.dtsi"
   9 #include "mt6380.dtsi"
  10
  11 / {
  12         model = "TP-Link TL-XDR3230 v1";
  13         compatible = "tplink,tl-xdr3230-v1", "mediatek,mt7622";
  14
  15         aliases {
  16                 ethernet0 = &gmac0;
  17                 label-mac-device = &gmac0;
  18                 led-boot = &led_status;
  19                 led-failsafe = &led_status;
  20                 led-running = &led_status;
  21                 led-upgrade = &led_status;
  22                 serial0 = &uart0;
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 root=/dev/fit0";
  28                 rootdisk = <&rootdisk>;
  29         };
  30
  31         cpus {
  32                 cpu@0 {
  33                         proc-supply = <&mt6380_vcpu_reg>;
  34                         sram-supply = <&mt6380_vm_reg>;
  35                 };
  36
  37                 cpu@1 {
  38                         proc-supply = <&mt6380_vcpu_reg>;
  39                         sram-supply = <&mt6380_vm_reg>;
  40                 };
  41         };
  42
  43         gpio-leds {
  44                 compatible = "gpio-leds";
  45                 led_status: green_status {
  46                         function = LED_FUNCTION_STATUS;
  47                         color = <LED_COLOR_ID_GREEN>;
  48                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  49                         default-state = "on";
  50                 };
  51
  52                 red_status {
  53                         function = LED_FUNCTION_STATUS;
  54                         color = <LED_COLOR_ID_RED>;
  55                         gpios = <&pio 90 GPIO_ACTIVE_HIGH>;
  56                 };
  57         };
  58
  59         gpio-keys {
  60                 compatible = "gpio-keys";
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 /* It seems that reset isn't connected to any MT7622 GPIO. Here's the WPS button. */
  65                 reset {
  66                         label = "reset";
  67                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  68                         linux,code = <KEY_RESTART>;
  69                 };
  70         };
  71
  72         rtkgsw: rtkgsw@0 {
  73                 compatible = "mediatek,rtk-gsw";
  74                 mediatek,ethsys = <&ethsys>;
  75                 mediatek,mdio = <&mdio>;
  76                 mediatek,reset-pin = <&pio 54 0>;
  77                 status = "okay";
  78         };
  79 };
  80
  81 &eth {
  82         status = "okay";
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&eth_pins>;
  85
  86         gmac0: mac@0 {
  87                 compatible = "mediatek,eth-mac";
  88                 reg = <0>;
  89                 nvmem-cells = <&macaddr_factory_4>;
  90                 nvmem-cell-names = "mac-address";
  91                 phy-connection-type = "2500base-x";
  92                 fixed-link {
  93                         speed = <2500>;
  94                         full-duplex;
  95                         pause;
  96                 };
  97         };
  98
  99         gmac1: mac@1 {
 100                 compatible = "mediatek,eth-mac";
 101                 reg = <1>;
 102                 phy-mode = "rgmii";
 103                 nvmem-cells = <&macaddr_factory_4>;
 104                 nvmem-cell-names = "mac-address";
 105                 mac-address-increment = <1>;
 106                 fixed-link {
 107                         speed = <1000>;
 108                         full-duplex;
 109                         pause;
 110                 };
 111         };
 112
 113         mdio: mdio-bus {
 114                 #address-cells = <1>;
 115                 #size-cells = <0>;
 116         };
 117 };
 118
 119 &pcie0 {
 120         status = "okay";
 121
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&pcie0_pins>;
 124 };
 125
 126 &slot0 {
 127         mt7915@0,0 {
 128                 reg = <0x0000 0 0 0 0>;
 129                 mediatek,mtd-eeprom = <&factory 0x1000>;
 130                 ieee80211-freq-limit = <5000000 6000000>;
 131         };
 132 };
 133
 134 &pio {
 135         epa_elna_pins: epa-elna-pins {
 136                 mux {
 137                         function = "antsel";
 138                         groups = "antsel0", "antsel1", "antsel2", "antsel3",
 139                                 "antsel4", "antsel5", "antsel6", "antsel7",
 140                                 "antsel8", "antsel9", "antsel12", "antsel13",
 141                                 "antsel14", "antsel15", "antsel16", "antsel17";
 142                 };
 143         };
 144
 145         eth_pins: eth-pins {
 146                 mux {
 147                         function = "eth";
 148                         groups = "mdc_mdio", "rgmii_via_gmac2";
 149                 };
 150         };
 151
 152         pcie0_pins: pcie0-pins {
 153                 mux {
 154                         function = "pcie";
 155                         groups = "pcie0_pad_perst",
 156                                  "pcie0_0_waken",
 157                                  "pcie0_0_clkreq";
 158                 };
 159         };
 160
 161         pmic_bus_pins: pmic-bus-pins {
 162                 mux {
 163                         function = "pmic";
 164                         groups = "pmic_bus";
 165                 };
 166         };
 167
 168         spi_nor_pins: spi-nor-pins {
 169                 mux {
 170                         function = "flash";
 171                         groups = "spi_nor";
 172                 };
 173         };
 174
 175         uart0_pins: uart0-pins {
 176                 mux {
 177                         function = "uart";
 178                         groups = "uart0_0_tx_rx";
 179                 };
 180         };
 181
 182         watchdog_pins: watchdog-pins {
 183                 mux {
 184                         function = "watchdog";
 185                         groups = "watchdog";
 186                 };
 187         };
 188 };
 189
 190 &pwrap {
 191         status = "okay";
 192
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&pmic_bus_pins>;
 195 };
 196
 197 &nor_flash {
 198         status = "okay";
 199
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&spi_nor_pins>;
 202
 203         flash@0 {
 204                 compatible = "jedec,spi-nor";
 205                 reg = <0>;
 206                 spi-tx-bus-width = <4>;
 207                 spi-rx-bus-width = <4>;
 208                 spi-max-frequency = <50000000>;
 209
 210                 mtdparts: partitions {
 211                         compatible = "fixed-partitions";
 212                         #address-cells = <1>;
 213                         #size-cells = <1>;
 214
 215                         partition@0 {
 216                                 label = "bl2";
 217                                 reg = <0x0 0x20000>;
 218                                 read-only;
 219                         };
 220
 221                         partition@20000 {
 222                                 label = "fip";
 223                                 reg = <0x20000 0x40000>;
 224                                 read-only;
 225                         };
 226
 227                         partition@60000 {
 228                                 label = "u-boot-env";
 229                                 reg = <0x60000 0x10000>;
 230                         };
 231
 232                         factory: partition@70000 {
 233                                 label = "factory";
 234                                 reg = <0x70000 0x10000>;
 235                                 read-only;
 236                         };
 237
 238                         rootdisk: partition@80000 {
 239                                 compatible = "denx,fit";
 240                                 label = "firmware";
 241                                 reg = <0x80000 0>;
 242                         };
 243                 };
 244         };
 245 };
 246
 247 &rtc {
 248         status = "disabled";
 249 };
 250
 251 &uart0 {
 252         status = "okay";
 253
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&uart0_pins>;
 256 };
 257
 258 &watchdog {
 259         status = "okay";
 260
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&watchdog_pins>;
 263 };
 264
 265 &wmac {
 266         status = "okay";
 267
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&epa_elna_pins>;
 270         mediatek,mtd-eeprom = <&factory 0x0>;
 271 };
 272
 273 &factory {
 274         compatible = "nvmem-cells";
 275         #address-cells = <1>;
 276         #size-cells = <1>;
 277
 278         macaddr_factory_4: macaddr@4 {
 279                 reg = <0x4 0x6>;
 280         };
 281 };