mediatek: use mac-base
[openwrt/staging/hauke.git] / target / linux / mediatek / dts / mt7623a-unielec-u7623-02.dtsi
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /*
3 * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
4 */
5
6 #include <dt-bindings/input/input.h>
7 #include "mt7623.dtsi"
8 #include "mt6323.dtsi"
9
10 / {
11 compatible = "unielec,u7623-02", "mediatek,mt7623";
12
13 aliases {
14 serial0 = &uart2;
15 ethernet0 = &gmac0;
16 mmc0 = &mmc0;
17 led-boot = &led3_green;
18 led-failsafe = &led3_green;
19 led-running = &led3_green;
20 led-upgrade = &led3_green;
21 };
22
23 chosen {
24 stdout-path = "serial0:115200n8";
25 };
26
27 cpus {
28 cpu@0 {
29 proc-supply = <&mt6323_vproc_reg>;
30 };
31
32 cpu@1 {
33 proc-supply = <&mt6323_vproc_reg>;
34 };
35
36 cpu@2 {
37 proc-supply = <&mt6323_vproc_reg>;
38 };
39
40 cpu@3 {
41 proc-supply = <&mt6323_vproc_reg>;
42 };
43 };
44
45 reg_1p8v: regulator-1p8v {
46 compatible = "regulator-fixed";
47 regulator-name = "fixed-1.8V";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 regulator-boot-on;
51 regulator-always-on;
52 };
53
54 reg_3p3v: regulator-3p3v {
55 compatible = "regulator-fixed";
56 regulator-name = "fixed-3.3V";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-boot-on;
60 regulator-always-on;
61 };
62
63 reg_5v: regulator-5v {
64 compatible = "regulator-fixed";
65 regulator-name = "fixed-5V";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
68 regulator-boot-on;
69 regulator-always-on;
70 };
71
72 gpio-keys {
73 compatible = "gpio-keys";
74 pinctrl-names = "default";
75 pinctrl-0 = <&key_pins_a>;
76
77 factory {
78 label = "factory";
79 linux,code = <KEY_RESTART>;
80 gpios = <&pio 256 GPIO_ACTIVE_LOW>;
81 };
82 };
83
84 leds {
85 compatible = "gpio-leds";
86 pinctrl-names = "default";
87 pinctrl-0 = <&led_pins_unielec>;
88
89 led3_green: led3 {
90 label = "u7623-01:green:led3";
91 gpios = <&pio 14 GPIO_ACTIVE_LOW>;
92 };
93
94 led4 {
95 label = "u7623-01:green:led4";
96 gpios = <&pio 15 GPIO_ACTIVE_LOW>;
97 };
98 };
99 };
100
101 &crypto {
102 status = "okay";
103 };
104
105 &eth {
106 status = "okay";
107
108 gmac0: mac@0 {
109 compatible = "mediatek,eth-mac";
110 reg = <0>;
111 phy-mode = "trgmii";
112
113 fixed-link {
114 speed = <1000>;
115 full-duplex;
116 pause;
117 };
118 };
119
120 mdio: mdio-bus {
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 mt7530: switch@0 {
125 compatible = "mediatek,mt7530";
126 };
127 };
128 };
129
130 &mt7530 {
131 compatible = "mediatek,mt7530";
132 #address-cells = <1>;
133 #size-cells = <0>;
134 reg = <0>;
135 pinctrl-names = "default";
136 mediatek,mcm;
137 resets = <&ethsys 2>;
138 reset-names = "mcm";
139 core-supply = <&mt6323_vpa_reg>;
140 io-supply = <&mt6323_vemc3v3_reg>;
141
142 dsa,mii-bus = <&mdio>;
143
144 ports {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 reg = <0>;
148
149 port@0 {
150 reg = <0>;
151 label = "lan0";
152 cpu = <&cpu_port0>;
153 };
154
155 port@1 {
156 reg = <1>;
157 label = "lan1";
158 cpu = <&cpu_port0>;
159 };
160
161 port@2 {
162 reg = <2>;
163 label = "lan2";
164 cpu = <&cpu_port0>;
165 };
166
167 port@3 {
168 reg = <3>;
169 label = "lan3";
170 cpu = <&cpu_port0>;
171 };
172
173 port@4 {
174 reg = <4>;
175 label = "wan";
176 cpu = <&cpu_port0>;
177 };
178
179 cpu_port0: port@6 {
180 reg = <6>;
181 ethernet = <&gmac0>;
182 phy-mode = "trgmii";
183
184 fixed-link {
185 speed = <1000>;
186 full-duplex;
187 };
188 };
189 };
190 };
191
192 &mmc0 {
193 pinctrl-names = "default", "state_uhs";
194 pinctrl-0 = <&mmc0_pins_default>;
195 pinctrl-1 = <&mmc0_pins_uhs>;
196 status = "okay";
197 bus-width = <8>;
198 max-frequency = <50000000>;
199 cap-mmc-highspeed;
200 vmmc-supply = <&reg_3p3v>;
201 vqmmc-supply = <&reg_1p8v>;
202 non-removable;
203 };
204
205 &pio {
206 key_pins_a: keys-alt {
207 pins-keys {
208 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
209 <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
210 input-enable;
211 };
212 };
213
214 led_pins_unielec: leds-unielec {
215 pins-leds {
216 pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
217 <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
218 };
219 };
220
221 mmc0_pins_default: mmc0default {
222 pins_cmd_dat {
223 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
224 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
225 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
226 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
227 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
228 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
229 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
230 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
231 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
232 input-enable;
233 bias-pull-up;
234 };
235
236 pins_clk {
237 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
238 bias-pull-down;
239 };
240
241 pins_rst {
242 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
243 bias-pull-up;
244 };
245 };
246
247 mmc0_pins_uhs: mmc0 {
248 pins_cmd_dat {
249 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
250 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
251 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
252 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
253 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
254 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
255 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
256 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
257 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
258 input-enable;
259 drive-strength = <MTK_DRIVE_2mA>;
260 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
261 };
262
263 pins_clk {
264 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
265 drive-strength = <MTK_DRIVE_2mA>;
266 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
267 };
268
269 pins_rst {
270 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
271 bias-pull-up;
272 };
273 };
274
275 pcie_default: pcie_pin_default {
276 pins_cmd_dat {
277 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
278 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
279 bias-disable;
280 };
281 };
282 };
283
284 &pwm {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pwm_pins_a>;
287 status = "okay";
288 };
289
290 &pwrap {
291 mt6323 {
292 mt6323led: led {
293 compatible = "mediatek,mt6323-led";
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 led@0 {
298 reg = <0>;
299 label = "led0";
300 };
301 };
302 };
303 };
304
305 &mt6323keys {
306 mediatek,long-press-mode = <0>;
307 };
308
309 &uart2 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&uart2_pins_b>;
312 status = "okay";
313 };
314
315 &usb1 {
316 vusb33-supply = <&reg_3p3v>;
317 vbus-supply = <&reg_3p3v>;
318 status = "okay";
319 };
320
321 &u3phy1 {
322 status = "okay";
323 };
324
325 &u3phy2 {
326 status = "okay";
327 mediatek,phy-switch = <&hifsys>;
328 };
329
330 &pcie {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pcie_default>;
333 status = "okay";
334
335 pcie@0,0 {
336 status = "okay";
337 };
338
339 pcie@1,0 {
340 status = "okay";
341 };
342
343 pcie@2,0 {
344 status = "okay";
345 };
346 };
347
348 &pcie0_phy {
349 status = "okay";
350 };
351
352 &pcie1_phy {
353 status = "okay";
354 };
355