1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
10 model = "Cetron CT3003";
11 compatible = "cetron,ct3003", "mediatek,mt7981";
15 led-boot = &led_status_red;
16 led-failsafe = &led_status_red;
17 led-running = &led_status_green;
18 led-upgrade = &led_status_green;
22 stdout-path = "serial0:115200n8";
26 reg = <0 0x40000000 0 0x10000000>;
30 compatible = "gpio-keys";
34 linux,code = <KEY_RESTART>;
35 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
40 linux,code = <KEY_WPS_BUTTON>;
41 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
46 compatible = "gpio-leds";
48 led_status_red: led_status_red {
50 gpios = <&pio 3 GPIO_ACTIVE_LOW>;
53 led_status_green: led_status_green {
54 label = "green:status";
55 gpios = <&pio 7 GPIO_ACTIVE_LOW>;
64 compatible = "mediatek,eth-mac";
66 phy-mode = "2500base-x";
68 nvmem-cells = <&macaddr_art_0>;
69 nvmem-cell-names = "mac-address";
81 compatible = "mediatek,mt7531";
83 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
85 #interrupt-cells = <1>;
86 interrupt-parent = <&pio>;
87 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&spi0_flash_pins>;
97 compatible = "spi-nand";
102 spi-max-frequency = <52000000>;
103 spi-tx-bus-width = <4>;
104 spi-rx-bus-width = <4>;
107 mediatek,bmt-max-ratio = <1>;
108 mediatek,bmt-max-reserved-blocks = <64>;
111 compatible = "fixed-partitions";
112 #address-cells = <1>;
117 reg = <0x0000000 0x0100000>;
122 label = "u-boot-env";
123 reg = <0x0100000 0x0080000>;
128 reg = <0x0180000 0x0100000>;
132 compatible = "fixed-layout";
133 #address-cells = <1>;
136 macaddr_art_0: macaddr@0 {
142 factory: partition@280000 {
144 reg = <0x0280000 0x0100000>;
150 reg = <0x0380000 0x0200000>;
156 reg = <0x0580000 0x2000000>;
160 label = "ubi_backup";
161 reg = <0x2580000 0x2000000>;
165 label = "Config_backup";
166 reg = <0x4580000 0x0400000>;
174 #address-cells = <1>;
200 phy-mode = "2500base-x";
212 spi0_flash_pins: spi0-pins {
215 groups = "spi0", "spi0_wp_hold";
219 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
220 drive-strength = <MTK_DRIVE_8mA>;
221 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
225 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
226 drive-strength = <MTK_DRIVE_8mA>;
227 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
243 mediatek,mtd-eeprom = <&factory 0x0>;