1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
10 model = "JCG Q30 PRO";
11 compatible = "jcg,q30-pro", "mediatek,mt7981";
15 label-mac-device = &gmac0;
16 led-boot = &led_status_red;
17 led-failsafe = &led_status_red;
18 led-running = &led_status_blue;
19 led-upgrade = &led_status_blue;
23 stdout-path = "serial0:115200n8";
27 reg = <0 0x40000000 0 0x10000000>;
31 compatible = "gpio-keys";
35 linux,code = <KEY_RESTART>;
36 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
41 compatible = "gpio-leds";
45 gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
48 led_status_blue: blue {
49 label = "blue:status";
50 gpios = <&pio 13 GPIO_ACTIVE_LOW>;
59 compatible = "mediatek,eth-mac";
61 phy-mode = "2500base-x";
63 nvmem-cells = <&macaddr_lan>;
64 nvmem-cell-names = "mac-address";
76 compatible = "mediatek,mt7531";
78 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
80 #interrupt-cells = <1>;
81 interrupt-parent = <&pio>;
82 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&spi0_flash_pins>;
92 compatible = "spi-nand";
97 spi-max-frequency = <52000000>;
98 spi-tx-bus-width = <4>;
99 spi-rx-bus-width = <4>;
102 compatible = "fixed-partitions";
103 #address-cells = <1>;
108 reg = <0x0000000 0x0100000>;
113 label = "u-boot-env";
114 reg = <0x0100000 0x0080000>;
117 factory: partition@180000 {
119 reg = <0x0180000 0x0200000>;
125 reg = <0x0380000 0x0200000>;
131 reg = <0x0580000 0x7000000>;
139 #address-cells = <1>;
145 nvmem-cells = <&macaddr_wan>;
146 nvmem-cell-names = "mac-address";
167 phy-mode = "2500base-x";
179 spi0_flash_pins: spi0-pins {
182 groups = "spi0", "spi0_wp_hold";
186 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
187 drive-strength = <8>;
188 mediatek,pull-up-adv = <0>; /* bias-disable */
192 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
193 drive-strength = <8>;
194 mediatek,pull-up-adv = <0>; /* bias-disable */
210 mediatek,mtd-eeprom = <&factory 0x0>;
214 compatible = "nvmem-cells";
215 #address-cells = <1>;
218 macaddr_wan: macaddr@a0024 {
222 macaddr_lan: macaddr@a002a {