1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
12 led-boot = &led_system_yellow;
13 led-failsafe = &led_system_yellow;
14 led-running = &led_system_blue;
15 led-upgrade = &led_system_yellow;
19 stdout-path = "serial0:115200n8";
23 reg = <0 0x40000000 0 0x10000000>;
27 compatible = "gpio-keys";
31 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
32 linux,code = <KEY_RESTART>;
37 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
39 linux,input-type = <EV_SW>;
44 compatible = "gpio-leds";
46 led_system_blue: system_blue {
47 label = "blue:system";
48 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
51 led_system_yellow: system_yellow {
52 label = "yellow:system";
53 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
57 label = "blue:network";
58 gpios = <&pio 11 GPIO_ACTIVE_LOW>;
62 label = "yellow:network";
63 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
72 compatible = "mediatek,eth-mac";
74 phy-mode = "2500base-x";
76 nvmem-cells = <&macaddr_factory_4>;
77 nvmem-cell-names = "mac-address";
78 mac-address-increment = <(-1)>;
90 compatible = "mediatek,mt7531";
92 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
94 #interrupt-cells = <1>;
95 interrupt-parent = <&pio>;
96 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
102 #address-cells = <1>;
128 phy-mode = "2500base-x";
140 pinctrl-names = "default";
141 pinctrl-0 = <&spi0_flash_pins>;
145 #address-cells = <1>;
147 compatible = "spi-nand";
150 spi-max-frequency = <52000000>;
151 spi-tx-buswidth = <4>;
152 spi-rx-buswidth = <4>;
154 partitions: partitions {
155 compatible = "fixed-partitions";
156 #address-cells = <1>;
161 reg = <0x00 0x100000>;
167 reg = <0x100000 0x40000>;
172 reg = <0x140000 0x40000>;
175 factory: partition@180000 {
177 reg = <0x180000 0x200000>;
180 compatible = "nvmem-cells";
181 #address-cells = <1>;
184 macaddr_factory_4: macaddr@4 {
191 reg = <0x380000 0x200000>;
197 reg = <0x580000 0x40000>;
203 reg = <0x5c0000 0x40000>;
209 reg = <0x7600000 0x40000>;
217 spi0_flash_pins: spi0-pins {
220 groups = "spi0", "spi0_wp_hold";
224 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
225 drive-strength = <MTK_DRIVE_8mA>;
226 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
230 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
231 drive-strength = <MTK_DRIVE_8mA>;
232 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
240 mediatek,mtd-eeprom = <&factory 0x0>;