1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 model = "Zbtlink ZBT-Z8102AX";
9 compatible = "zbtlink,zbt-z8102ax", "mediatek,mt7981";
13 led-boot = &led_status_green;
14 led-failsafe = &led_status_red;
15 led-running = &led_status_green;
16 led-upgrade = &led_status_green;
17 label-mac-device = &gmac0;
21 stdout-path = "serial0:115200n8";
22 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 loglevel=8";
26 reg = <0 0x40000000 0 0x40000000>;
30 compatible = "gpio-keys";
34 linux,code = <KEY_RESTART>;
35 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
41 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
47 gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
52 compatible = "gpio-leds";
56 gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
57 color = <LED_COLOR_ID_RED>;
58 function = LED_FUNCTION_STATUS;
61 led_status_green: green {
62 label = "green:status";
63 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
64 color = <LED_COLOR_ID_GREEN>;
65 function = LED_FUNCTION_STATUS;
69 label = "blue:status";
70 gpios = <&pio 11 GPIO_ACTIVE_LOW>;
71 color = <LED_COLOR_ID_BLUE>;
72 function = LED_FUNCTION_STATUS;
77 gpios = <&pio 8 GPIO_ACTIVE_LOW>;
78 color = <LED_COLOR_ID_BLUE>;
79 function = LED_FUNCTION_USB;
80 function-enumerator = <0>;
85 gpios = <&pio 14 GPIO_ACTIVE_LOW>;
86 color = <LED_COLOR_ID_BLUE>;
87 function = LED_FUNCTION_USB;
88 function-enumerator = <1>;
93 compatible = "linux,wdt-gpio";
94 gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
96 hw_margin_ms = <1000>;
100 compatible = "gpio-export";
104 gpio-export,name = "pcie_power";
105 gpio-export,output = <1>;
106 gpios = <&pio 3 GPIO_ACTIVE_HIGH>;
110 gpio-export,name = "5g1";
111 gpio-export,output = <1>;
112 gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
116 gpio-export,name = "5g2";
117 gpio-export,output = <1>;
118 gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
122 gpio-export,name = "sim1";
123 gpio-export,output = <1>;
124 gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
128 gpio-export,name = "sim2";
129 gpio-export,output = <1>;
130 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
140 compatible = "mediatek,eth-mac";
142 phy-mode = "2500base-x";
143 phy-handle = <&phy0>;
145 nvmem-cell-names = "mac-address";
146 nvmem-cells = <&macaddr_factory_4 2>;
157 compatible = "mediatek,eth-mac";
160 phy-handle = <&int_gbe_phy>;
162 nvmem-cell-names = "mac-address";
163 nvmem-cells = <&macaddr_factory_4 3>;
169 compatible = "mediatek,mt7531";
171 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
172 interrupt-controller;
173 #interrupt-cells = <1>;
174 interrupt-parent = <&pio>;
175 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&spi0_flash_pins>;
185 compatible = "spi-nand";
186 #address-cells = <1>;
190 spi-max-frequency = <52000000>;
191 spi-tx-bus-width = <4>;
192 spi-rx-bus-width = <4>;
195 mediatek,bmt-max-ratio = <1>;
196 mediatek,bmt-max-reserved-blocks = <64>;
199 compatible = "fixed-partitions";
200 #address-cells = <1>;
205 reg = <0x0000000 0x0100000>;
210 label = "u-boot-env";
211 reg = <0x100000 0x80000>;
216 reg = <0x180000 0x200000>;
220 compatible = "fixed-layout";
221 #address-cells = <1>;
224 eeprom_factory: eeprom@0 {
228 macaddr_factory_4: macaddr@4 {
229 compatible = "mac-base";
231 #nvmem-cell-cells = <1>;
238 reg = <0x380000 0x200000>;
244 reg = <0x580000 0x4000000>;
252 #address-cells = <1>;
279 phy-mode = "2500base-x";
291 spi0_flash_pins: spi0-pins {
294 groups = "spi0", "spi0_wp_hold";
298 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
299 drive-strength = <8>;
300 bias-pull-up = <103>;
304 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
305 drive-strength = <8>;
306 bias-pull-down = <103>;
330 nvmem-cells = <&eeprom_factory>;
331 nvmem-cell-names = "eeprom";