1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 model = "Zbtlink ZBT-Z8102AX";
9 compatible = "zbtlink,zbt-z8102ax", "mediatek,mt7981";
13 led-boot = &led_status_green;
14 led-failsafe = &led_status_red;
15 led-running = &led_status_green;
16 led-upgrade = &led_status_green;
17 label-mac-device = &gmac0;
21 stdout-path = "serial0:115200n8";
22 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 loglevel=8";
26 reg = <0 0x40000000 0 0x40000000>;
30 compatible = "gpio-keys";
34 linux,code = <KEY_RESTART>;
35 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
41 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
47 gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
52 compatible = "gpio-leds";
55 gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
56 color = <LED_COLOR_ID_RED>;
57 function = LED_FUNCTION_STATUS;
60 led_status_green: green {
61 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
62 color = <LED_COLOR_ID_GREEN>;
63 function = LED_FUNCTION_STATUS;
67 gpios = <&pio 11 GPIO_ACTIVE_LOW>;
68 color = <LED_COLOR_ID_BLUE>;
69 function = LED_FUNCTION_STATUS;
73 gpios = <&pio 8 GPIO_ACTIVE_LOW>;
74 color = <LED_COLOR_ID_BLUE>;
75 function = LED_FUNCTION_USB;
76 function-enumerator = <0>;
80 gpios = <&pio 14 GPIO_ACTIVE_LOW>;
81 color = <LED_COLOR_ID_BLUE>;
82 function = LED_FUNCTION_USB;
83 function-enumerator = <1>;
88 compatible = "linux,wdt-gpio";
89 gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
91 hw_margin_ms = <1000>;
95 compatible = "gpio-export";
99 gpio-export,name = "pcie_power";
100 gpio-export,output = <1>;
101 gpios = <&pio 3 GPIO_ACTIVE_HIGH>;
105 gpio-export,name = "5g1";
106 gpio-export,output = <1>;
107 gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
111 gpio-export,name = "5g2";
112 gpio-export,output = <1>;
113 gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
117 gpio-export,name = "sim1";
118 gpio-export,output = <1>;
119 gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
123 gpio-export,name = "sim2";
124 gpio-export,output = <1>;
125 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
135 compatible = "mediatek,eth-mac";
137 phy-mode = "2500base-x";
139 nvmem-cell-names = "mac-address";
140 nvmem-cells = <&macaddr_factory_4 2>;
151 compatible = "mediatek,eth-mac";
154 phy-handle = <&int_gbe_phy>;
156 nvmem-cell-names = "mac-address";
157 nvmem-cells = <&macaddr_factory_4 3>;
163 compatible = "mediatek,mt7531";
165 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
166 interrupt-controller;
167 #interrupt-cells = <1>;
168 interrupt-parent = <&pio>;
169 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&spi0_flash_pins>;
179 compatible = "spi-nand";
180 #address-cells = <1>;
184 spi-max-frequency = <52000000>;
185 spi-tx-bus-width = <4>;
186 spi-rx-bus-width = <4>;
189 mediatek,bmt-max-ratio = <1>;
190 mediatek,bmt-max-reserved-blocks = <64>;
193 compatible = "fixed-partitions";
194 #address-cells = <1>;
199 reg = <0x0000000 0x0100000>;
204 label = "u-boot-env";
205 reg = <0x100000 0x80000>;
210 reg = <0x180000 0x200000>;
214 compatible = "fixed-layout";
215 #address-cells = <1>;
218 eeprom_factory: eeprom@0 {
222 macaddr_factory_4: macaddr@4 {
223 compatible = "mac-base";
225 #nvmem-cell-cells = <1>;
232 reg = <0x380000 0x200000>;
238 reg = <0x580000 0x4000000>;
246 #address-cells = <1>;
273 phy-mode = "2500base-x";
285 spi0_flash_pins: spi0-pins {
288 groups = "spi0", "spi0_wp_hold";
292 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
293 drive-strength = <8>;
294 bias-pull-up = <103>;
298 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
299 drive-strength = <8>;
300 bias-pull-down = <103>;
324 nvmem-cells = <&eeprom_factory>;
325 nvmem-cell-names = "eeprom";