6bff786558be9ec2fd2218b30f8c019dc92a406e
[openwrt/staging/blocktrron.git] / target / linux / mediatek / dts / mt7986a-acer-predator-w6.dts
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7
8 #include "mt7986a.dtsi"
9
10 / {
11 model = "Acer Predator W6";
12 compatible = "acer,predator-w6", "mediatek,mt7986a";
13
14 aliases {
15 serial0 = &uart0;
16 led-boot = &led_status;
17 led-failsafe = &led_status;
18 led-running = &led_status;
19 led-upgrade = &led_status;
20 };
21
22 chosen {
23 stdout-path = "serial0:115200n8";
24 bootargs = "dm-mod.create=\"dm-verity,,,ro,0 31544 verity 1 PARTLABEL=rootfs PARTLABEL=rootfs 4096 4096 3943 3944 sha256 2f969fa9e9e4e20b37746f22633e85b178f5db7c143e11f92733a704299cc933 2dd56e34b15c6c84573cf26c4392028421061d2c808975217b45e9a5b49d2087\" rootfstype=squashfs,ext4 rootwait root=/dev/mmcblk0p6 fstools_ignore_partname=1";
25 };
26
27 memory {
28 reg = <0 0x40000000 0 0x20000000>;
29 };
30
31 reg_1p8v: regulator-1p8v {
32 compatible = "regulator-fixed";
33 regulator-name = "fixed-1.8V";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <1800000>;
36 regulator-boot-on;
37 regulator-always-on;
38 };
39
40 reg_3p3v: regulator-3p3v {
41 compatible = "regulator-fixed";
42 regulator-name = "fixed-3.3V";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
48
49 reg_5v: regulator-5v {
50 compatible = "regulator-fixed";
51 regulator-name = "fixed-5V";
52 regulator-min-microvolt = <5000000>;
53 regulator-max-microvolt = <5000000>;
54 regulator-boot-on;
55 regulator-always-on;
56 };
57
58 gpio-keys {
59 compatible = "gpio-keys";
60
61 factory {
62 label = "factory";
63 linux,code = <KEY_RESTART>;
64 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
65 };
66
67 wps {
68 label = "wps";
69 linux,code = <KEY_WPS_BUTTON>;
70 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
71 };
72 };
73
74
75 leds {
76 compatible = "gpio-leds";
77
78 led_status: led@0 {
79 label = "ant0:red";
80 gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
81 default-state = "off";
82 };
83
84 led@1 {
85 label = "ant0:green";
86 gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
87 default-state = "off";
88 };
89
90 led@2 {
91 label = "ant0:blue";
92 gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
93 default-state = "off";
94 };
95
96 led@3 {
97 label = "ant1:red";
98 gpios = <&pio 35 GPIO_ACTIVE_HIGH>;
99 default-state = "off";
100 };
101
102 led@4 {
103 label = "ant1:green";
104 gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
105 default-state = "off";
106 };
107
108 led@5 {
109 label = "ant1:blue";
110 gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
111 default-state = "off";
112 };
113
114 led@6 {
115 label = "ant2:red";
116 gpios = <&pio 38 GPIO_ACTIVE_HIGH>;
117 default-state = "off";
118 };
119
120 led@7 {
121 label = "ant2:green";
122 gpios = <&pio 37 GPIO_ACTIVE_HIGH>;
123 default-state = "off";
124 };
125
126 led@8 {
127 label = "ant2:blue";
128 gpios = <&pio 26 GPIO_ACTIVE_HIGH>;
129 default-state = "off";
130 };
131
132 led@9 {
133 label = "ant3:red";
134 gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
135 default-state = "off";
136 };
137
138 led@10 {
139 label = "ant3:green";
140 gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
141 default-state = "off";
142 };
143
144 led@11 {
145 label = "ant3:blue";
146 gpios = <&pio 23 GPIO_ACTIVE_HIGH>;
147 default-state = "off";
148 };
149
150 led@12 {
151 label = "ant4:red";
152 gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
153 default-state = "off";
154 };
155
156 led@13 {
157 label = "ant4:green";
158 gpios = <&pio 27 GPIO_ACTIVE_HIGH>;
159 default-state = "off";
160 };
161
162 led@14 {
163 label = "ant4:blue";
164 gpios = <&pio 32 GPIO_ACTIVE_HIGH>;
165 default-state = "off";
166 };
167
168 led@15 {
169 label = "ant5:red";
170 gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
171 default-state = "off";
172 };
173
174 led@16 {
175 label = "ant5:green";
176 gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
177 default-state = "off";
178 };
179
180 led@17 {
181 label = "ant5:blue";
182 gpios = <&pio 43 GPIO_ACTIVE_HIGH>;
183 default-state = "off";
184 };
185 };
186
187 };
188
189 &eth {
190 status = "okay";
191
192 gmac0: mac@0 {
193 /* LAN */
194 compatible = "mediatek,eth-mac";
195 reg = <0>;
196 phy-mode = "2500base-x";
197
198 fixed-link {
199 speed = <2500>;
200 full-duplex;
201 pause;
202 };
203 };
204
205 gmac1: mac@1 {
206 /* WAN */
207 compatible = "mediatek,eth-mac";
208 reg = <1>;
209 phy-mode = "2500base-x";
210 phy-handle = <&phy6>;
211 };
212
213 mdio: mdio-bus {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 };
217 };
218
219 &mdio {
220 phy6: phy@6 {
221 compatible = "ethernet-phy-ieee802.3-c45";
222 reg = <6>;
223
224 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
225 reset-assert-us = <10000>;
226 reset-deassert-us = <10000>;
227
228 /* LED0: nc ; LED1: nc ; LED2: Amber ; LED3: Green */
229 mxl,led-config = <0x0 0x0 0x370 0x80>;
230 };
231
232 switch: switch@1f {
233 compatible = "mediatek,mt7531";
234 reg = <31>;
235
236 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
237 reset-assert-us = <10000>;
238 reset-deassert-us = <10000>;
239 };
240 };
241
242 &pio {
243 mmc0_pins_default: mmc0-pins {
244 mux {
245 function = "emmc";
246 groups = "emmc_51";
247 };
248 conf-cmd-dat {
249 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
250 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
251 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
252 input-enable;
253 drive-strength = <4>;
254 mediatek,pull-up-adv = <1>; /* pull-up 10K */
255 };
256 conf-clk {
257 pins = "EMMC_CK";
258 drive-strength = <6>;
259 mediatek,pull-down-adv = <2>; /* pull-down 50K */
260 };
261 conf-ds {
262 pins = "EMMC_DSL";
263 mediatek,pull-down-adv = <2>; /* pull-down 50K */
264 };
265 conf-rst {
266 pins = "EMMC_RSTB";
267 drive-strength = <4>;
268 mediatek,pull-up-adv = <1>; /* pull-up 10K */
269 };
270 };
271
272 mmc0_pins_uhs: mmc0-uhs-pins {
273 mux {
274 function = "emmc";
275 groups = "emmc_51";
276 };
277 conf-cmd-dat {
278 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
279 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
280 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
281 input-enable;
282 drive-strength = <4>;
283 mediatek,pull-up-adv = <1>; /* pull-up 10K */
284 };
285 conf-clk {
286 pins = "EMMC_CK";
287 drive-strength = <6>;
288 mediatek,pull-down-adv = <2>; /* pull-down 50K */
289 };
290 conf-ds {
291 pins = "EMMC_DSL";
292 mediatek,pull-down-adv = <2>; /* pull-down 50K */
293 };
294 conf-rst {
295 pins = "EMMC_RSTB";
296 drive-strength = <4>;
297 mediatek,pull-up-adv = <1>; /* pull-up 10K */
298 };
299 };
300
301 pcie_pins: pcie-pins {
302 mux {
303 function = "pcie";
304 groups = "pcie_pereset";
305 };
306 };
307
308 wf_2g_5g_pins: wf_2g_5g-pins {
309 mux {
310 function = "wifi";
311 groups = "wf_2g", "wf_5g";
312 };
313 conf {
314 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
315 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
316 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
317 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
318 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
319 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
320 "WF1_TOP_CLK", "WF1_TOP_DATA";
321 drive-strength = <4>;
322 };
323 };
324
325 wf_dbdc_pins: wf-dbdc-pins {
326 mux {
327 function = "wifi";
328 groups = "wf_dbdc";
329 };
330 conf {
331 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
332 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
333 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
334 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
335 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
336 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
337 "WF1_TOP_CLK", "WF1_TOP_DATA";
338 drive-strength = <4>;
339 };
340 };
341 };
342
343 &switch {
344 ports {
345 #address-cells = <1>;
346 #size-cells = <0>;
347
348 port@0 {
349 reg = <0>;
350 label = "game";
351 };
352
353 port@1 {
354 reg = <1>;
355 label = "lan1";
356 };
357
358 port@2 {
359 reg = <2>;
360 label = "lan2";
361 };
362
363 port@3 {
364 reg = <3>;
365 label = "lan3";
366 };
367
368 port@6 {
369 reg = <6>;
370 label = "cpu";
371 ethernet = <&gmac0>;
372 phy-mode = "2500base-x";
373
374 fixed-link {
375 speed = <2500>;
376 full-duplex;
377 pause;
378 };
379 };
380 };
381
382 mdio {
383 #address-cells = <1>;
384 #size-cells = <0>;
385
386 phy@0 {
387 reg = <0>;
388
389 mediatek,led-config = <
390 0x21 0x8009 /* BASIC_CTRL */
391 0x22 0x0c00 /* ON_DURATION */
392 0x23 0x1400 /* BLINK_DURATION */
393 0x24 0xc001 /* LED0_ON_CTRL */
394 0x25 0x0000 /* LED0_BLINK_CTRL */
395 0x26 0xc007 /* LED1_ON_CTRL */
396 0x27 0x003f /* LED1_BLINK_CTRL */
397 >;
398 };
399
400 phy@1 {
401 reg = <1>;
402
403 mediatek,led-config = <
404 0x21 0x8009 /* BASIC_CTRL */
405 0x22 0x0c00 /* ON_DURATION */
406 0x23 0x1400 /* BLINK_DURATION */
407 0x24 0xc001 /* LED0_ON_CTRL */
408 0x25 0x0000 /* LED0_BLINK_CTRL */
409 0x26 0xc007 /* LED1_ON_CTRL */
410 0x27 0x003f /* LED1_BLINK_CTRL */
411 >;
412 };
413
414 phy@2 {
415 reg = <2>;
416
417 mediatek,led-config = <
418 0x21 0x8009 /* BASIC_CTRL */
419 0x22 0x0c00 /* ON_DURATION */
420 0x23 0x1400 /* BLINK_DURATION */
421 0x24 0xc001 /* LED0_ON_CTRL */
422 0x25 0x0000 /* LED0_BLINK_CTRL */
423 0x26 0xc007 /* LED1_ON_CTRL */
424 0x27 0x003f /* LED1_BLINK_CTRL */
425 >;
426 };
427
428 phy@3 {
429 reg = <3>;
430
431 mediatek,led-config = <
432 0x21 0x8009 /* BASIC_CTRL */
433 0x22 0x0c00 /* ON_DURATION */
434 0x23 0x1400 /* BLINK_DURATION */
435 0x24 0xc001 /* LED0_ON_CTRL */
436 0x25 0x0000 /* LED0_BLINK_CTRL */
437 0x26 0xc007 /* LED1_ON_CTRL */
438 0x27 0x003f /* LED1_BLINK_CTRL */
439 >;
440 };
441 };
442 };
443
444 &wifi {
445 status = "okay";
446 pinctrl-names = "default", "dbdc";
447 pinctrl-0 = <&wf_2g_5g_pins>;
448 pinctrl-1 = <&wf_dbdc_pins>;
449 };
450
451 &trng {
452 status = "okay";
453 };
454
455 &watchdog {
456 status = "okay";
457 };
458
459 &crypto {
460 status = "okay";
461 };
462
463 &uart0 {
464 status = "okay";
465 };
466
467 &ssusb {
468 vusb33-supply = <&reg_3p3v>;
469 vbus-supply = <&reg_5v>;
470 status = "okay";
471 };
472
473 &usb_phy {
474 status = "okay";
475 };
476
477 &mmc0 {
478 status = "okay";
479 pinctrl-names = "default", "state_uhs";
480 pinctrl-0 = <&mmc0_pins_default>;
481 pinctrl-1 = <&mmc0_pins_uhs>;
482 bus-width = <0x08>;
483 max-frequency = <200000000>;
484 cap-mmc-highspeed;
485 mmc-hs200-1_8v;
486 mmc-hs400-1_8v;
487 hs400-ds-delay = <0x14014>;
488 vmmc-supply = <&reg_3p3v>;
489 vqmmc-supply = <&reg_1p8v>;
490 non-removable;
491 no-sd;
492 no-sdio;
493 };
494
495 &pcie {
496 pinctrl-names = "default";
497 pinctrl-0 = <&pcie_pins>;
498 status = "okay";
499 };
500
501 &pcie_phy {
502 status = "okay";
503 };