target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "ASUS TUF-AX4200";
  12         compatible = "asus,tuf-ax4200", "mediatek,mt7986a";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 led-boot = &led_system;
  17                 led-failsafe = &led_system;
  18                 led-running = &led_system;
  19                 led-upgrade = &led_system;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs-override = "ubi.mtd=UBI_DEV";
  25         };
  26
  27         memory {
  28                 reg = <0 0x40000000 0 0x20000000>;
  29         };
  30
  31         keys {
  32                 compatible = "gpio-keys";
  33
  34                 reset {
  35                         label = "reset";
  36                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_RESTART>;
  38                 };
  39
  40                 mesh {
  41                         label = "wps";
  42                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  43                         linux,code = <KEY_WPS_BUTTON>;
  44                 };
  45         };
  46
  47         leds {
  48                 compatible = "gpio-leds";
  49
  50                 wlan24 {
  51                         label = "white:wlan24";
  52                         gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
  53                         linux,default-trigger = "phy0tpt";
  54                 };
  55
  56                 wlan5 {
  57                         label = "white:wlan5";
  58                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  59                         linux,default-trigger = "phy1tpt";
  60                 };
  61
  62                 led_system: system {
  63                         label = "white:system";
  64                         gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
  65                 };
  66
  67                 wan-red {
  68                         label = "red:wan";
  69                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  70                 };
  71         };
  72
  73         reg_3p3v: regulator-3p3v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "fixed-3.3V";
  76                 regulator-min-microvolt = <3300000>;
  77                 regulator-max-microvolt = <3300000>;
  78                 regulator-boot-on;
  79                 regulator-always-on;
  80         };
  81
  82         reg_5v: regulator-5v {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "fixed-5V";
  85                 regulator-min-microvolt = <5000000>;
  86                 regulator-max-microvolt = <5000000>;
  87                 regulator-boot-on;
  88                 regulator-always-on;
  89         };
  90 };
  91
  92 &crypto {
  93         status = "okay";
  94 };
  95
  96 &eth {
  97         status = "okay";
  98
  99         gmac0: mac@0 {
 100                 /* LAN */
 101                 compatible = "mediatek,eth-mac";
 102                 reg = <0>;
 103                 phy-mode = "2500base-x";
 104
 105                 fixed-link {
 106                         speed = <2500>;
 107                         full-duplex;
 108                         pause;
 109                 };
 110         };
 111
 112         gmac1: mac@1 {
 113                 /* WAN */
 114                 compatible = "mediatek,eth-mac";
 115                 reg = <1>;
 116                 phy-mode = "2500base-x";
 117                 phy-handle = <&phy6>;
 118         };
 119
 120         mdio: mdio-bus {
 121                 #address-cells = <1>;
 122                 #size-cells = <0>;
 123         };
 124 };
 125
 126 &mdio {
 127         phy6: phy@6 {
 128                 compatible = "ethernet-phy-ieee802.3-c45";
 129                 reg = <6>;
 130
 131                 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 132                 reset-assert-us = <10000>;
 133                 reset-deassert-us = <10000>;
 134
 135                 /* LED0: CONN (WAN white) */
 136                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 137         };
 138
 139         switch: switch@0 {
 140                 compatible = "mediatek,mt7531";
 141                 reg = <31>;
 142
 143                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 144                 reset-assert-us = <10000>;
 145                 reset-deassert-us = <10000>;
 146         };
 147 };
 148
 149 &pio {
 150         spi_flash_pins: spi-flash-pins-33-to-38 {
 151                 mux {
 152                         function = "spi";
 153                         groups = "spi0", "spi0_wp_hold";
 154                 };
 155                 conf-pu {
 156                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 157                         drive-strength = <8>;
 158                         mediatek,pull-up-adv = <0>; /* bias-disable */
 159                 };
 160                 conf-pd {
 161                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 162                         drive-strength = <8>;
 163                         mediatek,pull-down-adv = <0>; /* bias-disable */
 164                 };
 165         };
 166
 167         wf_2g_5g_pins: wf_2g_5g-pins {
 168                 mux {
 169                         function = "wifi";
 170                         groups = "wf_2g", "wf_5g";
 171                 };
 172                 conf {
 173                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 174                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 175                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 176                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 177                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 178                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 179                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 180                         drive-strength = <4>;
 181                 };
 182         };
 183
 184         wf_dbdc_pins: wf-dbdc-pins {
 185                 mux {
 186                         function = "wifi";
 187                         groups = "wf_dbdc";
 188                 };
 189                 conf {
 190                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 191                                 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 192                                 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 193                                 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 194                                 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 195                                 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 196                                 "WF1_TOP_CLK", "WF1_TOP_DATA";
 197                         drive-strength = <4>;
 198                 };
 199         };
 200 };
 201
 202 &spi0 {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&spi_flash_pins>;
 205         status = "okay";
 206
 207         spi_nand_flash: flash@0 {
 208                 compatible = "spi-nand";
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 reg = <0>;
 212
 213                 spi-max-frequency = <20000000>;
 214                 spi-tx-bus-width = <4>;
 215                 spi-rx-bus-width = <4>;
 216
 217                 partitions: partitions {
 218                         compatible = "fixed-partitions";
 219                         #address-cells = <1>;
 220                         #size-cells = <1>;
 221
 222                         partition@0 {
 223                                 label = "bootloader";
 224                                 reg = <0x0 0x400000>;
 225                                 read-only;
 226                         };
 227
 228                         partition@400000 {
 229                                 label = "UBI_DEV";
 230                                 reg = <0x400000 0xfc00000>;
 231                         };
 232                 };
 233         };
 234 };
 235
 236 &switch {
 237         ports {
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240
 241                 port@1 {
 242                         reg = <1>;
 243                         label = "lan1";
 244                 };
 245
 246                 port@2 {
 247                         reg = <2>;
 248                         label = "lan2";
 249                 };
 250
 251                 port@3 {
 252                         reg = <3>;
 253                         label = "lan3";
 254                 };
 255
 256                 port@4 {
 257                         reg = <4>;
 258                         label = "lan4";
 259                 };
 260
 261                 port@6 {
 262                         reg = <6>;
 263                         label = "cpu";
 264                         ethernet = <&gmac0>;
 265                         phy-mode = "2500base-x";
 266
 267                         fixed-link {
 268                                 speed = <2500>;
 269                                 full-duplex;
 270                                 pause;
 271                         };
 272                 };
 273         };
 274
 275         mdio {
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278
 279                 phy@1 {
 280                         reg = <1>;
 281
 282                         mediatek,led-config = <
 283                                 0x21 0x8009 /* BASIC_CTRL */
 284                                 0x22 0x0c00 /* ON_DURATION */
 285                                 0x23 0x1400 /* BLINK_DURATION */
 286                                 0x24 0x8000 /* LED0_ON_CTRL */
 287                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 288                                 0x26 0xc007 /* LED1_ON_CTRL */
 289                                 0x27 0x003f /* LED1_BLINK_CTRL */
 290                         >;
 291                 };
 292
 293                 phy@2 {
 294                         reg = <2>;
 295
 296                         mediatek,led-config = <
 297                                 0x21 0x8009 /* BASIC_CTRL */
 298                                 0x22 0x0c00 /* ON_DURATION */
 299                                 0x23 0x1400 /* BLINK_DURATION */
 300                                 0x24 0x8000 /* LED0_ON_CTRL */
 301                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 302                                 0x26 0xc007 /* LED1_ON_CTRL */
 303                                 0x27 0x003f /* LED1_BLINK_CTRL */
 304                         >;
 305                 };
 306
 307                 phy@3 {
 308                         reg = <3>;
 309
 310                         mediatek,led-config = <
 311                                 0x21 0x8009 /* BASIC_CTRL */
 312                                 0x22 0x0c00 /* ON_DURATION */
 313                                 0x23 0x1400 /* BLINK_DURATION */
 314                                 0x24 0x8000 /* LED0_ON_CTRL */
 315                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 316                                 0x26 0xc007 /* LED1_ON_CTRL */
 317                                 0x27 0x003f /* LED1_BLINK_CTRL */
 318                         >;
 319                 };
 320
 321                 phy@4 {
 322                         reg = <4>;
 323
 324                         mediatek,led-config = <
 325                                 0x21 0x8009 /* BASIC_CTRL */
 326                                 0x22 0x0c00 /* ON_DURATION */
 327                                 0x23 0x1400 /* BLINK_DURATION */
 328                                 0x24 0x8000 /* LED0_ON_CTRL */
 329                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 330                                 0x26 0xc007 /* LED1_ON_CTRL */
 331                                 0x27 0x003f /* LED1_BLINK_CTRL */
 332                         >;
 333                 };
 334         };
 335 };
 336
 337 &watchdog {
 338         status = "okay";
 339 };
 340
 341 &wifi {
 342         status = "okay";
 343         pinctrl-names = "default", "dbdc";
 344         pinctrl-0 = <&wf_2g_5g_pins>;
 345         pinctrl-1 = <&wf_dbdc_pins>;
 346 };
 347
 348 &trng {
 349         status = "okay";
 350 };
 351
 352 &uart0 {
 353         status = "okay";
 354 };
 355
 356 &ssusb {
 357         vusb33-supply = <&reg_3p3v>;
 358         vbus-supply = <&reg_5v>;
 359         status = "okay";
 360 };
 361
 362 &usb_phy {
 363         status = "okay";
 364 };