1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
8 #include "mt7986a.dtsi"
11 model = "ASUS TUF-AX4200";
12 compatible = "asus,tuf-ax4200", "mediatek,mt7986a";
16 label-mac-device = &gmac0;
17 led-boot = &led_system;
18 led-failsafe = &led_system;
19 led-running = &led_system;
20 led-upgrade = &led_system;
24 stdout-path = "serial0:115200n8";
25 bootargs-override = "";
29 reg = <0 0x40000000 0 0x20000000>;
33 compatible = "gpio-keys";
37 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
38 linux,code = <KEY_RESTART>;
43 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_WPS_BUTTON>;
49 compatible = "gpio-leds";
52 label = "white:wlan24";
53 gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
54 linux,default-trigger = "phy0tpt";
58 label = "white:wlan5";
59 gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
60 linux,default-trigger = "phy1tpt";
64 label = "white:system";
65 gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
69 function = LED_FUNCTION_WAN;
70 color = <LED_COLOR_ID_RED>;
71 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
75 reg_3p3v: regulator-3p3v {
76 compatible = "regulator-fixed";
77 regulator-name = "fixed-3.3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
84 reg_5v: regulator-5v {
85 compatible = "regulator-fixed";
86 regulator-name = "fixed-5V";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
103 compatible = "mediatek,eth-mac";
105 nvmem-cells = <&macaddr_factory_4>;
106 nvmem-cell-names = "mac-address";
107 phy-mode = "2500base-x";
118 compatible = "mediatek,eth-mac";
120 phy-mode = "2500base-x";
121 phy-handle = <&phy6>;
125 #address-cells = <1>;
132 compatible = "ethernet-phy-ieee802.3-c45";
135 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
136 reset-assert-us = <10000>;
137 reset-deassert-us = <10000>;
139 /* LED0: CONN (WAN white) */
140 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
144 compatible = "mediatek,mt7531";
147 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
148 reset-assert-us = <10000>;
149 reset-deassert-us = <10000>;
154 spi_flash_pins: spi-flash-pins-33-to-38 {
157 groups = "spi0", "spi0_wp_hold";
160 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
161 drive-strength = <8>;
162 mediatek,pull-up-adv = <0>; /* bias-disable */
165 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
166 drive-strength = <8>;
167 mediatek,pull-down-adv = <0>; /* bias-disable */
171 wf_2g_5g_pins: wf_2g_5g-pins {
174 groups = "wf_2g", "wf_5g";
177 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
178 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
179 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
180 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
181 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
182 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
183 "WF1_TOP_CLK", "WF1_TOP_DATA";
184 drive-strength = <4>;
188 wf_dbdc_pins: wf-dbdc-pins {
194 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
195 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
196 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
197 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
198 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
199 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
200 "WF1_TOP_CLK", "WF1_TOP_DATA";
201 drive-strength = <4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&spi_flash_pins>;
211 spi_nand_flash: flash@0 {
212 compatible = "spi-nand";
213 #address-cells = <1>;
217 spi-max-frequency = <20000000>;
218 spi-tx-bus-width = <4>;
219 spi-rx-bus-width = <4>;
222 * ASUS bootloader tries to replace the partitions defined in
223 * Device Tree and by that also deletes all additional properties
224 * needed for UBI and NVMEM-on-UBI.
225 * Prevent this from happening by tricking the loader to delete and
226 * replace a bait node instead.
229 compatible = "u-boot-dummy-partitions";
230 #address-cells = <1>;
240 compatible = "fixed-partitions";
241 #address-cells = <1>;
245 reg = <0x0 0x400000>;
246 label = "bootloader";
251 compatible = "linux,ubi";
252 reg = <0x400000 0xfc00000>;
256 ubi_factory: ubi-volume-factory {
267 compatible = "fixed-layout";
268 #address-cells = <1>;
271 eeprom_factory_0: eeprom@0 {
275 macaddr_factory_4: macaddr@4 {
283 #address-cells = <1>;
310 phy-mode = "2500base-x";
321 #address-cells = <1>;
327 mediatek,led-config = <
328 0x21 0x8009 /* BASIC_CTRL */
329 0x22 0x0c00 /* ON_DURATION */
330 0x23 0x1400 /* BLINK_DURATION */
331 0x24 0x8000 /* LED0_ON_CTRL */
332 0x25 0x0000 /* LED0_BLINK_CTRL */
333 0x26 0xc007 /* LED1_ON_CTRL */
334 0x27 0x003f /* LED1_BLINK_CTRL */
341 mediatek,led-config = <
342 0x21 0x8009 /* BASIC_CTRL */
343 0x22 0x0c00 /* ON_DURATION */
344 0x23 0x1400 /* BLINK_DURATION */
345 0x24 0x8000 /* LED0_ON_CTRL */
346 0x25 0x0000 /* LED0_BLINK_CTRL */
347 0x26 0xc007 /* LED1_ON_CTRL */
348 0x27 0x003f /* LED1_BLINK_CTRL */
355 mediatek,led-config = <
356 0x21 0x8009 /* BASIC_CTRL */
357 0x22 0x0c00 /* ON_DURATION */
358 0x23 0x1400 /* BLINK_DURATION */
359 0x24 0x8000 /* LED0_ON_CTRL */
360 0x25 0x0000 /* LED0_BLINK_CTRL */
361 0x26 0xc007 /* LED1_ON_CTRL */
362 0x27 0x003f /* LED1_BLINK_CTRL */
369 mediatek,led-config = <
370 0x21 0x8009 /* BASIC_CTRL */
371 0x22 0x0c00 /* ON_DURATION */
372 0x23 0x1400 /* BLINK_DURATION */
373 0x24 0x8000 /* LED0_ON_CTRL */
374 0x25 0x0000 /* LED0_BLINK_CTRL */
375 0x26 0xc007 /* LED1_ON_CTRL */
376 0x27 0x003f /* LED1_BLINK_CTRL */
387 nvmem-cells = <&eeprom_factory_0>;
388 nvmem-cell-names = "eeprom";
389 pinctrl-0 = <&wf_2g_5g_pins>;
390 pinctrl-1 = <&wf_dbdc_pins>;
391 pinctrl-names = "default", "dbdc";
404 vusb33-supply = <®_3p3v>;
405 vbus-supply = <®_5v>;