target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "ASUS TUF-AX6000";
  12         compatible = "asus,tuf-ax6000", "mediatek,mt7986a";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 led-boot = &led_system;
  17                 led-failsafe = &led_system;
  18                 led-running = &led_system;
  19                 led-upgrade = &led_system;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs-override = "ubi.mtd=UBI_DEV";
  25         };
  26
  27         memory {
  28                 reg = <0 0x40000000 0 0x20000000>;
  29         };
  30
  31         keys {
  32                 compatible = "gpio-keys";
  33
  34                 reset {
  35                         label = "reset";
  36                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_RESTART>;
  38                 };
  39
  40                 mesh {
  41                         label = "wps";
  42                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  43                         linux,code = <KEY_WPS_BUTTON>;
  44                 };
  45         };
  46
  47         leds {
  48                 compatible = "gpio-leds";
  49
  50                 wlan {
  51                         label = "white:wlan";
  52                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  53                         linux,default-trigger = "phy1tpt";
  54                 };
  55
  56                 led_system: system {
  57                         label = "white:system";
  58                         gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
  59                 };
  60
  61                 wan-red {
  62                         label = "red:wan";
  63                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  64                 };
  65
  66                 cover-blue {
  67                         label = "blue:cover";
  68                         gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  69                 };
  70         };
  71
  72         reg_3p3v: regulator-3p3v {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "fixed-3.3V";
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 regulator-boot-on;
  78                 regulator-always-on;
  79         };
  80
  81         reg_5v: regulator-5v {
  82                 compatible = "regulator-fixed";
  83                 regulator-name = "fixed-5V";
  84                 regulator-min-microvolt = <5000000>;
  85                 regulator-max-microvolt = <5000000>;
  86                 regulator-boot-on;
  87                 regulator-always-on;
  88         };
  89 };
  90
  91 &crypto {
  92         status = "okay";
  93 };
  94
  95 &eth {
  96         status = "okay";
  97
  98         gmac0: mac@0 {
  99                 /* LAN */
 100                 compatible = "mediatek,eth-mac";
 101                 reg = <0>;
 102                 phy-mode = "2500base-x";
 103
 104                 fixed-link {
 105                         speed = <2500>;
 106                         full-duplex;
 107                         pause;
 108                 };
 109         };
 110
 111         gmac1: mac@1 {
 112                 /* WAN */
 113                 compatible = "mediatek,eth-mac";
 114                 reg = <1>;
 115                 phy-mode = "2500base-x";
 116                 phy-handle = <&phy6>;
 117         };
 118
 119         mdio: mdio-bus {
 120                 #address-cells = <1>;
 121                 #size-cells = <0>;
 122         };
 123 };
 124
 125 &mdio {
 126         reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 127         reset-delay-us = <50000>;
 128         reset-post-delay-us = <20000>;
 129
 130         phy5: phy@5 {
 131                 compatible = "ethernet-phy-ieee802.3-c45";
 132                 reg = <5>;
 133
 134                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 135         };
 136
 137         phy6: phy@6 {
 138                 compatible = "ethernet-phy-ieee802.3-c45";
 139                 reg = <6>;
 140
 141                 /* LED0: CONN (WAN white) */
 142                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 143         };
 144
 145         switch: switch@1f {
 146                 compatible = "mediatek,mt7531";
 147                 reg = <31>;
 148
 149                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 150                 reset-assert-us = <10000>;
 151                 reset-deassert-us = <10000>;
 152         };
 153 };
 154
 155 &pio {
 156         spi_flash_pins: spi-flash-pins-33-to-38 {
 157                 mux {
 158                         function = "spi";
 159                         groups = "spi0", "spi0_wp_hold";
 160                 };
 161                 conf-pu {
 162                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 163                         drive-strength = <8>;
 164                         mediatek,pull-up-adv = <0>; /* bias-disable */
 165                 };
 166                 conf-pd {
 167                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 168                         drive-strength = <8>;
 169                         mediatek,pull-down-adv = <0>; /* bias-disable */
 170                 };
 171         };
 172
 173         wf_2g_5g_pins: wf_2g_5g-pins {
 174                 mux {
 175                         function = "wifi";
 176                         groups = "wf_2g", "wf_5g";
 177                 };
 178                 conf {
 179                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 180                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 181                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 182                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 183                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 184                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 185                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 186                         drive-strength = <4>;
 187                 };
 188         };
 189
 190         wf_dbdc_pins: wf-dbdc-pins {
 191                 mux {
 192                         function = "wifi";
 193                         groups = "wf_dbdc";
 194                 };
 195                 conf {
 196                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 197                                 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 198                                 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 199                                 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 200                                 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 201                                 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 202                                 "WF1_TOP_CLK", "WF1_TOP_DATA";
 203                         drive-strength = <4>;
 204                 };
 205         };
 206 };
 207
 208 &pcie_phy {
 209         status = "okay";
 210 };
 211
 212 &spi0 {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&spi_flash_pins>;
 215         status = "okay";
 216
 217         spi_nand_flash: flash@0 {
 218                 compatible = "spi-nand";
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221                 reg = <0>;
 222
 223                 spi-max-frequency = <20000000>;
 224                 spi-tx-bus-width = <4>;
 225                 spi-rx-bus-width = <4>;
 226
 227                 partitions: partitions {
 228                         compatible = "fixed-partitions";
 229                         #address-cells = <1>;
 230                         #size-cells = <1>;
 231
 232                         partition@0 {
 233                                 label = "bootloader";
 234                                 reg = <0x0 0x400000>;
 235                                 read-only;
 236                         };
 237
 238                         partition@400000 {
 239                                 label = "UBI_DEV";
 240                                 reg = <0x400000 0xfc00000>;
 241                         };
 242                 };
 243         };
 244 };
 245
 246 &switch {
 247         ports {
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250
 251                 port@1 {
 252                         reg = <4>;
 253                         label = "lan1";
 254                 };
 255
 256                 port@2 {
 257                         reg = <3>;
 258                         label = "lan2";
 259                 };
 260
 261                 port@3 {
 262                         reg = <2>;
 263                         label = "lan3";
 264                 };
 265
 266                 port@4 {
 267                         reg = <1>;
 268                         label = "lan4";
 269                 };
 270
 271                 port@5 {
 272                         reg = <5>;
 273                         label = "lan5";
 274                         phy-mode = "2500base-x";
 275                         phy-handle = <&phy5>;
 276
 277                 };
 278
 279                 port@6 {
 280                         reg = <6>;
 281                         label = "cpu";
 282                         ethernet = <&gmac0>;
 283                         phy-mode = "2500base-x";
 284
 285                         fixed-link {
 286                                 speed = <2500>;
 287                                 full-duplex;
 288                                 pause;
 289                         };
 290                 };
 291         };
 292
 293         mdio {
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296
 297                 phy@1 {
 298                         reg = <1>;
 299
 300                         mediatek,led-config = <
 301                                 0x21 0x8009 /* BASIC_CTRL */
 302                                 0x22 0x0c00 /* ON_DURATION */
 303                                 0x23 0x1400 /* BLINK_DURATION */
 304                                 0x24 0x8000 /* LED0_ON_CTRL */
 305                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 306                                 0x26 0xc007 /* LED1_ON_CTRL */
 307                                 0x27 0x003f /* LED1_BLINK_CTRL */
 308                         >;
 309                 };
 310
 311                 phy@2 {
 312                         reg = <2>;
 313
 314                         mediatek,led-config = <
 315                                 0x21 0x8009 /* BASIC_CTRL */
 316                                 0x22 0x0c00 /* ON_DURATION */
 317                                 0x23 0x1400 /* BLINK_DURATION */
 318                                 0x24 0x8000 /* LED0_ON_CTRL */
 319                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 320                                 0x26 0xc007 /* LED1_ON_CTRL */
 321                                 0x27 0x003f /* LED1_BLINK_CTRL */
 322                         >;
 323                 };
 324
 325                 phy@3 {
 326                         reg = <3>;
 327
 328                         mediatek,led-config = <
 329                                 0x21 0x8009 /* BASIC_CTRL */
 330                                 0x22 0x0c00 /* ON_DURATION */
 331                                 0x23 0x1400 /* BLINK_DURATION */
 332                                 0x24 0x8000 /* LED0_ON_CTRL */
 333                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 334                                 0x26 0xc007 /* LED1_ON_CTRL */
 335                                 0x27 0x003f /* LED1_BLINK_CTRL */
 336                         >;
 337                 };
 338
 339                 phy@4 {
 340                         reg = <4>;
 341
 342                         mediatek,led-config = <
 343                                 0x21 0x8009 /* BASIC_CTRL */
 344                                 0x22 0x0c00 /* ON_DURATION */
 345                                 0x23 0x1400 /* BLINK_DURATION */
 346                                 0x24 0x8000 /* LED0_ON_CTRL */
 347                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 348                                 0x26 0xc007 /* LED1_ON_CTRL */
 349                                 0x27 0x003f /* LED1_BLINK_CTRL */
 350                         >;
 351                 };
 352         };
 353 };
 354
 355 &watchdog {
 356         status = "okay";
 357 };
 358
 359 &wifi {
 360         status = "okay";
 361         pinctrl-names = "default", "dbdc";
 362         pinctrl-0 = <&wf_2g_5g_pins>;
 363         pinctrl-1 = <&wf_dbdc_pins>;
 364 };
 365
 366 &trng {
 367         status = "okay";
 368 };
 369
 370 &uart0 {
 371         status = "okay";
 372 };
 373
 374 &ssusb {
 375         vusb33-supply = <&reg_3p3v>;
 376         vbus-supply = <&reg_5v>;
 377         status = "okay";
 378 };
 379
 380 &usb_phy {
 381         status = "okay";
 382 };