1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
8 #include "mt7986a.dtsi"
11 model = "ASUS TUF-AX6000";
12 compatible = "asus,tuf-ax6000", "mediatek,mt7986a";
16 label-mac-device = &gmac0;
17 led-boot = &led_system;
18 led-failsafe = &led_system;
19 led-running = &led_system;
20 led-upgrade = &led_system;
24 stdout-path = "serial0:115200n8";
25 bootargs-override = "";
29 reg = <0 0x40000000 0 0x20000000>;
33 compatible = "gpio-keys";
37 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
38 linux,code = <KEY_RESTART>;
43 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_WPS_BUTTON>;
49 compatible = "gpio-leds";
52 function = LED_FUNCTION_WLAN;
53 color = <LED_COLOR_ID_WHITE>;
54 gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
55 linux,default-trigger = "phy1tpt";
59 label = "white:system";
60 gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
64 function = LED_FUNCTION_WAN;
65 color = <LED_COLOR_ID_RED>;
66 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
71 gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
75 reg_3p3v: regulator-3p3v {
76 compatible = "regulator-fixed";
77 regulator-name = "fixed-3.3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
84 reg_5v: regulator-5v {
85 compatible = "regulator-fixed";
86 regulator-name = "fixed-5V";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
103 compatible = "mediatek,eth-mac";
105 nvmem-cells = <&macaddr_factory_4>;
106 nvmem-cell-names = "mac-address";
107 phy-mode = "2500base-x";
118 compatible = "mediatek,eth-mac";
120 phy-mode = "2500base-x";
121 phy-handle = <&phy6>;
125 #address-cells = <1>;
131 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
132 reset-delay-us = <50000>;
133 reset-post-delay-us = <20000>;
136 compatible = "ethernet-phy-ieee802.3-c45";
140 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
144 compatible = "ethernet-phy-ieee802.3-c45";
147 /* LED0: CONN (WAN white) */
148 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
152 compatible = "mediatek,mt7531";
155 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
156 reset-assert-us = <10000>;
157 reset-deassert-us = <10000>;
162 spi_flash_pins: spi-flash-pins-33-to-38 {
165 groups = "spi0", "spi0_wp_hold";
168 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
169 drive-strength = <8>;
170 mediatek,pull-up-adv = <0>; /* bias-disable */
173 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
174 drive-strength = <8>;
175 mediatek,pull-down-adv = <0>; /* bias-disable */
179 wf_2g_5g_pins: wf_2g_5g-pins {
182 groups = "wf_2g", "wf_5g";
185 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
186 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
187 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
188 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
189 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
190 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
191 "WF1_TOP_CLK", "WF1_TOP_DATA";
192 drive-strength = <4>;
196 wf_dbdc_pins: wf-dbdc-pins {
202 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
203 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
204 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
205 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
206 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
207 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
208 "WF1_TOP_CLK", "WF1_TOP_DATA";
209 drive-strength = <4>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&spi_flash_pins>;
223 spi_nand_flash: flash@0 {
224 compatible = "spi-nand";
226 #address-cells = <1>;
229 spi-max-frequency = <20000000>;
230 spi-tx-bus-width = <4>;
231 spi-rx-bus-width = <4>;
234 * ASUS bootloader tries to replace the partitions defined in
235 * Device Tree and by that also deletes all additional properties
236 * needed for UBI and NVMEM-on-UBI.
237 * Prevent this from happening by tricking the loader to delete and
238 * replace a bait node instead.
241 compatible = "u-boot-dummy-partitions";
242 #address-cells = <1>;
252 compatible = "fixed-partitions";
253 #address-cells = <1>;
257 reg = <0x0 0x400000>;
258 label = "bootloader";
263 compatible = "linux,ubi";
264 reg = <0x400000 0xfc00000>;
268 ubi_factory: ubi-volume-factory {
279 compatible = "fixed-layout";
280 #address-cells = <1>;
283 eeprom_factory_0: eeprom@0 {
287 macaddr_factory_4: macaddr@4 {
295 #address-cells = <1>;
321 phy-mode = "2500base-x";
322 phy-handle = <&phy5>;
330 phy-mode = "2500base-x";
341 #address-cells = <1>;
347 mediatek,led-config = <
348 0x21 0x8009 /* BASIC_CTRL */
349 0x22 0x0c00 /* ON_DURATION */
350 0x23 0x1400 /* BLINK_DURATION */
351 0x24 0x8000 /* LED0_ON_CTRL */
352 0x25 0x0000 /* LED0_BLINK_CTRL */
353 0x26 0xc007 /* LED1_ON_CTRL */
354 0x27 0x003f /* LED1_BLINK_CTRL */
361 mediatek,led-config = <
362 0x21 0x8009 /* BASIC_CTRL */
363 0x22 0x0c00 /* ON_DURATION */
364 0x23 0x1400 /* BLINK_DURATION */
365 0x24 0x8000 /* LED0_ON_CTRL */
366 0x25 0x0000 /* LED0_BLINK_CTRL */
367 0x26 0xc007 /* LED1_ON_CTRL */
368 0x27 0x003f /* LED1_BLINK_CTRL */
375 mediatek,led-config = <
376 0x21 0x8009 /* BASIC_CTRL */
377 0x22 0x0c00 /* ON_DURATION */
378 0x23 0x1400 /* BLINK_DURATION */
379 0x24 0x8000 /* LED0_ON_CTRL */
380 0x25 0x0000 /* LED0_BLINK_CTRL */
381 0x26 0xc007 /* LED1_ON_CTRL */
382 0x27 0x003f /* LED1_BLINK_CTRL */
389 mediatek,led-config = <
390 0x21 0x8009 /* BASIC_CTRL */
391 0x22 0x0c00 /* ON_DURATION */
392 0x23 0x1400 /* BLINK_DURATION */
393 0x24 0x8000 /* LED0_ON_CTRL */
394 0x25 0x0000 /* LED0_BLINK_CTRL */
395 0x26 0xc007 /* LED1_ON_CTRL */
396 0x27 0x003f /* LED1_BLINK_CTRL */
407 nvmem-cells = <&eeprom_factory_0>;
408 nvmem-cell-names = "eeprom";
409 pinctrl-names = "default", "dbdc";
410 pinctrl-0 = <&wf_2g_5g_pins>;
411 pinctrl-1 = <&wf_dbdc_pins>;
424 vusb33-supply = <®_3p3v>;
425 vbus-supply = <®_5v>;