1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/pinctrl/mt65xx.h>
8 #include "mt7986a.dtsi"
11 model = "GL.iNet GL-MT6000";
12 compatible = "glinet,gl-mt6000", "mediatek,mt7986a";
19 stdout-path = "serial0:115200n8";
20 bootargs-append = " root=PARTLABEL=rootfs rootwait";
23 reg_1p8v: regulator-1p8v {
24 compatible = "regulator-fixed";
25 regulator-name = "1.8vd";
26 regulator-min-microvolt = <1800000>;
27 regulator-max-microvolt = <1800000>;
32 reg_3p3v: regulator-3p3v {
33 compatible = "regulator-fixed";
34 regulator-name = "fixed-3.3V";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
42 compatible = "gpio-keys";
46 linux,code = <KEY_RESTART>;
47 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
52 compatible = "gpio-leds";
56 gpios = <&pio 38 GPIO_ACTIVE_LOW>;
61 label = "white:system";
62 gpios = <&pio 37 GPIO_ACTIVE_LOW>;
66 usb_vbus: regulator-usb-vbus {
67 compatible = "regulator-fixed";
68 regulator-name = "usb_vbus";
69 regulator-min-microvolt = <5000000>;
70 regulator-max-microvolt = <5000000>;
71 gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
81 compatible = "mediatek,eth-mac";
83 phy-mode = "2500base-x";
93 compatible = "mediatek,eth-mac";
95 phy-mode = "2500base-x";
100 #address-cells = <1>;
104 compatible = "ethernet-phy-ieee802.3-c45";
106 reset-assert-us = <100000>;
107 reset-deassert-us = <100000>;
108 reset-gpios = <&pio 10 GPIO_ACTIVE_LOW>;
109 interrupt-parent = <&pio>;
110 interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
111 realtek,aldps-enable;
114 phy7: ethernet-phy@7 {
115 compatible = "ethernet-phy-ieee802.3-c45";
117 reset-assert-us = <100000>;
118 reset-deassert-us = <100000>;
119 reset-gpios = <&pio 19 GPIO_ACTIVE_LOW>;
120 interrupt-parent = <&pio>;
121 interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
122 realtek,aldps-enable;
126 compatible = "mediatek,mt7531";
128 reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 interrupt-parent = <&pio>;
132 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
135 #address-cells = <1>;
161 phy-handle = <&phy7>;
162 phy-mode = "2500base-x";
168 phy-mode = "2500base-x";
182 wf_2g_5g_pins: wf_2g_5g-pins {
185 groups = "wf_2g", "wf_5g";
188 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
189 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
190 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
191 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
192 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
193 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
194 "WF1_TOP_CLK", "WF1_TOP_DATA";
195 drive-strength = <4>;
199 mmc0_pins_default: mmc0-pins {
205 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
206 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
207 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
209 drive-strength = <4>;
210 mediatek,pull-up-adv = <1>; /* pull-up 10K */
214 drive-strength = <6>;
215 mediatek,pull-down-adv = <2>; /* pull-down 50K */
219 mediatek,pull-down-adv = <2>; /* pull-down 50K */
223 drive-strength = <4>;
224 mediatek,pull-up-adv = <1>; /* pull-up 10K */
228 mmc0_pins_uhs: mmc0-uhs-pins {
234 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
235 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
236 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
238 drive-strength = <4>;
239 mediatek,pull-up-adv = <1>; /* pull-up 10K */
243 drive-strength = <6>;
244 mediatek,pull-down-adv = <2>; /* pull-down 50K */
248 mediatek,pull-down-adv = <2>; /* pull-down 50K */
252 drive-strength = <4>;
253 mediatek,pull-up-adv = <1>; /* pull-up 10K */
263 vusb33-supply = <®_3p3v>;
264 vbus-supply = <&usb_vbus>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&wf_2g_5g_pins>;
291 pinctrl-names = "default", "state_uhs";
292 pinctrl-0 = <&mmc0_pins_default>;
293 pinctrl-1 = <&mmc0_pins_uhs>;
295 max-frequency = <200000000>;
299 hs400-ds-delay = <0x14014>;
300 vmmc-supply = <®_3p3v>;
301 vqmmc-supply = <®_1p8v>;