1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/pinctrl/mt65xx.h>
8 #include "mt7986a.dtsi"
11 model = "GL.iNet GL-MT6000";
12 compatible = "glinet,gl-mt6000", "mediatek,mt7986a";
16 led-boot = &led_white;
17 led-failsafe = &led_white;
18 led-running = &led_blue;
19 led-upgrade = &led_white;
23 stdout-path = "serial0:115200n8";
24 bootargs-append = " root=PARTLABEL=rootfs rootwait";
27 reg_1p8v: regulator-1p8v {
28 compatible = "regulator-fixed";
29 regulator-name = "1.8vd";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
36 reg_3p3v: regulator-3p3v {
37 compatible = "regulator-fixed";
38 regulator-name = "fixed-3.3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
46 compatible = "gpio-keys";
50 linux,code = <KEY_RESTART>;
51 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
56 compatible = "gpio-leds";
60 gpios = <&pio 38 GPIO_ACTIVE_LOW>;
64 label = "white:system";
65 gpios = <&pio 37 GPIO_ACTIVE_LOW>;
69 usb_vbus: regulator-usb-vbus {
70 compatible = "regulator-fixed";
71 regulator-name = "usb_vbus";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
84 compatible = "mediatek,eth-mac";
86 phy-mode = "2500base-x";
96 compatible = "mediatek,eth-mac";
98 phy-mode = "2500base-x";
103 #address-cells = <1>;
107 compatible = "ethernet-phy-ieee802.3-c45";
109 reset-assert-us = <100000>;
110 reset-deassert-us = <100000>;
111 reset-gpios = <&pio 10 GPIO_ACTIVE_LOW>;
112 interrupt-parent = <&pio>;
113 interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
114 realtek,aldps-enable;
117 phy7: ethernet-phy@7 {
118 compatible = "ethernet-phy-ieee802.3-c45";
120 reset-assert-us = <100000>;
121 reset-deassert-us = <100000>;
122 reset-gpios = <&pio 19 GPIO_ACTIVE_LOW>;
123 interrupt-parent = <&pio>;
124 interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
125 realtek,aldps-enable;
129 compatible = "mediatek,mt7531";
131 reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 interrupt-parent = <&pio>;
135 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
138 #address-cells = <1>;
164 phy-handle = <&phy7>;
165 phy-mode = "2500base-x";
171 phy-mode = "2500base-x";
185 wf_2g_5g_pins: wf_2g_5g-pins {
188 groups = "wf_2g", "wf_5g";
191 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
192 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
193 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
194 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
195 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
196 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
197 "WF1_TOP_CLK", "WF1_TOP_DATA";
198 drive-strength = <4>;
202 mmc0_pins_default: mmc0-pins {
208 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
209 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
210 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
212 drive-strength = <4>;
213 mediatek,pull-up-adv = <1>; /* pull-up 10K */
217 drive-strength = <6>;
218 mediatek,pull-down-adv = <2>; /* pull-down 50K */
222 mediatek,pull-down-adv = <2>; /* pull-down 50K */
226 drive-strength = <4>;
227 mediatek,pull-up-adv = <1>; /* pull-up 10K */
231 mmc0_pins_uhs: mmc0-uhs-pins {
237 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
238 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
239 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
241 drive-strength = <4>;
242 mediatek,pull-up-adv = <1>; /* pull-up 10K */
246 drive-strength = <6>;
247 mediatek,pull-down-adv = <2>; /* pull-down 50K */
251 mediatek,pull-down-adv = <2>; /* pull-down 50K */
255 drive-strength = <4>;
256 mediatek,pull-up-adv = <1>; /* pull-up 10K */
266 vusb33-supply = <®_3p3v>;
267 vbus-supply = <&usb_vbus>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&wf_2g_5g_pins>;
294 pinctrl-names = "default", "state_uhs";
295 pinctrl-0 = <&mmc0_pins_default>;
296 pinctrl-1 = <&mmc0_pins_uhs>;
298 max-frequency = <200000000>;
302 hs400-ds-delay = <0x14014>;
303 vmmc-supply = <®_3p3v>;
304 vqmmc-supply = <®_1p8v>;