1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (C) 2023 Tianling Shen <cnsztl@immortalwrt.org>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
11 #include "mt7986a.dtsi"
14 model = "JDCloud RE-CP-03";
15 compatible = "jdcloud,re-cp-03", "mediatek,mt7986a";
19 led-failsafe = &red_led;
20 led-running = &green_led;
21 led-upgrade = &green_led;
26 stdout-path = "serial0:115200n8";
30 reg = <0 0x40000000 0 0x40000000>;
34 compatible = "gpio-keys";
39 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_RESTART>;
45 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
50 compatible = "gpio-leds";
53 color = <LED_COLOR_ID_BLUE>;
54 function = LED_FUNCTION_STATUS;
55 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
59 color = <LED_COLOR_ID_RED>;
60 function = LED_FUNCTION_STATUS;
61 gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
65 color = <LED_COLOR_ID_GREEN>;
66 function = LED_FUNCTION_STATUS;
67 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
71 reg_1p8v: regulator-1p8v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-1.8V";
74 regulator-min-microvolt = <1800000>;
75 regulator-max-microvolt = <1800000>;
80 reg_3p3v: regulator-3p3v {
81 compatible = "regulator-fixed";
82 regulator-name = "fixed-3.3V";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
98 compatible = "mediatek,eth-mac";
100 phy-mode = "2500base-x";
110 compatible = "mediatek,eth-mac";
112 phy-mode = "2500base-x";
113 phy-handle = <&phy6>;
117 #address-cells = <1>;
124 compatible = "ethernet-phy-ieee802.3-c45";
127 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
128 reset-assert-us = <10000>;
129 reset-deassert-us = <50000>;
130 realtek,aldps-enable;
134 compatible = "mediatek,mt7531";
136 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 interrupt-parent = <&pio>;
140 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
147 hs400-ds-delay = <0x14014>;
148 max-frequency = <200000000>;
154 pinctrl-names = "default", "state_uhs";
155 pinctrl-0 = <&mmc0_pins_default>;
156 pinctrl-1 = <&mmc0_pins_uhs>;
157 vmmc-supply = <®_3p3v>;
158 vqmmc-supply = <®_1p8v>;
163 mmc0_pins_default: mmc0-pins-default {
169 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
170 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
171 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
173 drive-strength = <4>;
174 mediatek,pull-up-adv = <1>;
178 drive-strength = <6>;
179 mediatek,pull-down-adv = <2>;
183 mediatek,pull-down-adv = <2>;
187 drive-strength = <4>;
188 mediatek,pull-up-adv = <1>;
192 mmc0_pins_uhs: mmc0-uhs-pins {
198 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
199 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
200 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
202 drive-strength = <4>;
203 mediatek,pull-up-adv = <1>;
207 drive-strength = <6>;
208 mediatek,pull-down-adv = <2>;
212 mediatek,pull-down-adv = <2>;
216 drive-strength = <4>;
217 mediatek,pull-up-adv = <1>;
221 wf_2g_5g_pins: wf-2g-5g-pins {
224 groups = "wf_2g", "wf_5g";
227 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
228 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
229 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
230 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
231 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
232 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
233 "WF1_TOP_CLK", "WF1_TOP_DATA";
234 drive-strength = <4>;
241 #address-cells = <1>;
267 phy-mode = "2500base-x";
291 pinctrl-names = "default";
292 pinctrl-0 = <&wf_2g_5g_pins>;