1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
6 #include "mt7986a.dtsi"
11 label-mac-device = &gmac0;
12 led-boot = &led_status_green;
13 led-failsafe = &led_status_red;
14 led-running = &led_status_green;
15 led-upgrade = &led_status_red;
19 stdout-path = "serial0:115200n8";
23 reg = <0 0x40000000 0 0x20000000>;
26 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
35 reg_5v: regulator-5v {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-5V";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
45 compatible = "gpio-keys";
49 linux,code = <KEY_RESTART>;
50 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
55 linux,code = <KEY_WPS_BUTTON>;
56 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
62 gpios = <&pio 11 GPIO_ACTIVE_LOW>;
67 compatible = "gpio-leds";
69 led_status_red: status_red {
71 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
74 led_status_green: status_green {
75 label = "green:status";
76 gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
80 label = "green:turbo";
81 gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
90 compatible = "mediatek,eth-mac";
92 phy-mode = "2500base-x";
94 nvmem-cells = <&macaddr_config_1c>;
95 nvmem-cell-names = "mac-address";
105 compatible = "mediatek,eth-mac";
107 phy-handle = <&phy7>;
108 phy-mode = "2500base-x";
110 nvmem-cells = <&macaddr_config_1c>;
111 nvmem-cell-names = "mac-address";
112 mac-address-increment = <1>;
116 #address-cells = <1>;
122 phy5: ethernet-phy@5 {
123 compatible = "ethernet-phy-ieee802.3-c45";
125 reset-assert-us = <100000>;
126 reset-deassert-us = <100000>;
127 reset-gpios = <&pio 13 GPIO_ACTIVE_LOW>;
128 realtek,aldps-enable;
131 phy7: ethernet-phy@7 {
132 compatible = "ethernet-phy-ieee802.3-c45";
134 reset-assert-us = <100000>;
135 reset-deassert-us = <100000>;
136 reset-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
137 realtek,aldps-enable;
141 compatible = "mediatek,mt7531";
143 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
144 interrupt-controller;
145 #interrupt-cells = <1>;
146 interrupt-parent = <&pio>;
147 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&spi_flash_pins>;
157 compatible = "spi-nand";
158 #address-cells = <1>;
162 spi-max-frequency = <20000000>;
163 spi-tx-buswidth = <4>;
164 spi-rx-buswidth = <4>;
167 compatible = "fixed-partitions";
168 #address-cells = <1>;
173 reg = <0x000000 0x0100000>;
177 config: partition@100000 {
179 reg = <0x100000 0x0060000>;
183 factory: partition@160000 {
185 reg = <0x160000 0x0060000>;
191 reg = <0x1c0000 0x01c0000>;
197 reg = <0x380000 0x0200000>;
203 reg = <0x580000 0x7800000>;
210 spi_flash_pins: spi-flash-pins-33-to-38 {
213 groups = "spi0", "spi0_wp_hold";
216 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
217 drive-strength = <8>;
218 mediatek,pull-up-adv = <0>; /* bias-disable */
221 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
222 drive-strength = <8>;
223 mediatek,pull-down-adv = <0>; /* bias-disable */
229 vusb33-supply = <®_3p3v>;
230 vbus-supply = <®_5v>;
243 mediatek,mtd-eeprom = <&factory 0x0>;
244 nvmem-cells = <&macaddr_config_1c>;
245 nvmem-cell-names = "mac-address";
246 mac-address-increment = <2>;
251 compatible = "nvmem-cells";
252 #address-cells = <1>;
255 macaddr_config_1c: macaddr@1c {