1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
8 #include "mt7986a.dtsi"
13 led-boot = &led_status_rgb;
14 led-failsafe = &led_status_rgb;
15 led-running = &led_status_rgb;
16 led-upgrade = &led_status_rgb;
20 stdout-path = "serial0:115200n8";
24 reg = <0 0x40000000 0 0x20000000>;
28 compatible = "gpio-keys";
32 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
33 linux,code = <KEY_RESTART>;
38 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
40 linux,input-type = <EV_SW>;
53 compatible = "mediatek,eth-mac";
55 phy-mode = "2500base-x";
57 nvmem-cells = <&macaddr_factory_4>;
58 nvmem-cell-names = "mac-address";
59 mac-address-increment = <(-1)>;
76 compatible = "mediatek,mt7531";
78 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
80 #interrupt-cells = <1>;
81 interrupt-parent = <&pio>;
82 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
87 spi_flash_pins: spi-flash-pins-33-to-38 {
90 groups = "spi0", "spi0_wp_hold";
93 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
95 mediatek,pull-up-adv = <0>; /* bias-disable */
98 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
100 mediatek,pull-down-adv = <0>; /* bias-disable */
104 spi_led_pins: spic-pins-29-to-32 {
111 wf_2g_5g_pins: wf_2g_5g-pins {
114 groups = "wf_2g", "wf_5g";
117 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
118 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
119 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
120 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
121 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
122 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
123 "WF1_TOP_CLK", "WF1_TOP_DATA";
124 drive-strength = <4>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&spi_flash_pins>;
134 spi_nand_flash: flash@0 {
135 compatible = "spi-nand";
136 #address-cells = <1>;
140 spi-max-frequency = <20000000>;
141 spi-tx-bus-width = <4>;
142 spi-rx-bus-width = <4>;
144 partitions: partitions {
145 compatible = "fixed-partitions";
146 #address-cells = <1>;
151 reg = <0x0 0x100000>;
157 reg = <0x100000 0x40000>;
162 reg = <0x140000 0x40000>;
165 factory: partition@180000 {
167 reg = <0x180000 0x200000>;
170 compatible = "nvmem-cells";
171 #address-cells = <1>;
174 macaddr_factory_4: macaddr@4 {
181 reg = <0x380000 0x200000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&spi_led_pins>;
194 #address-cells = <1>;
196 compatible = "worldsemi,ws2812b";
198 spi-max-frequency = <3000000>;
200 led_status_rgb: led@0 {
202 label = "rgb:status";
203 color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
206 led_network_rgb: led@1 {
208 label = "rgb:network";
209 color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
216 #address-cells = <1>;
242 phy-mode = "2500base-x";
267 pinctrl-names = "default";
268 pinctrl-0 = <&wf_2g_5g_pins>;
270 mediatek,mtd-eeprom = <&factory 0x0>;