target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         aliases {
  12                 serial0 = &uart0;
  13                 led-boot = &led_status_rgb;
  14                 led-failsafe = &led_status_rgb;
  15                 led-running = &led_status_rgb;
  16                 led-upgrade = &led_status_rgb;
  17         };
  18
  19         chosen {
  20                 stdout-path = "serial0:115200n8";
  21         };
  22
  23         memory {
  24                 reg = <0 0x40000000 0 0x20000000>;
  25         };
  26
  27         keys {
  28                 compatible = "gpio-keys";
  29
  30                 reset {
  31                         label = "reset";
  32                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  33                         linux,code = <KEY_RESTART>;
  34                 };
  35
  36                 mesh {
  37                         label = "mesh";
  38                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  39                         linux,code = <BTN_9>;
  40                         linux,input-type = <EV_SW>;
  41                 };
  42         };
  43 };
  44
  45 &eth {
  46         status = "okay";
  47
  48         gmac0: mac@0 {
  49                 compatible = "mediatek,eth-mac";
  50                 reg = <0>;
  51                 phy-mode = "2500base-x";
  52
  53                 nvmem-cells = <&macaddr_factory_4>;
  54                 nvmem-cell-names = "mac-address";
  55                 mac-address-increment = <(-1)>;
  56
  57                 fixed-link {
  58                         speed = <2500>;
  59                         full-duplex;
  60                         pause;
  61                 };
  62         };
  63
  64         mdio: mdio-bus {
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67         };
  68 };
  69
  70 &mdio {
  71         switch: switch@0 {
  72                 compatible = "mediatek,mt7531";
  73                 reg = <31>;
  74                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  75                 interrupt-controller;
  76                 #interrupt-cells = <1>;
  77                 interrupt-parent = <&pio>;
  78                 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  79         };
  80 };
  81
  82 &pio {
  83         spi_flash_pins: spi-flash-pins-33-to-38 {
  84                 mux {
  85                         function = "spi";
  86                         groups = "spi0", "spi0_wp_hold";
  87                 };
  88                 conf-pu {
  89                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  90                         drive-strength = <8>;
  91                         mediatek,pull-up-adv = <0>; /* bias-disable */
  92                 };
  93                 conf-pd {
  94                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  95                         drive-strength = <8>;
  96                         mediatek,pull-down-adv = <0>; /* bias-disable */
  97                 };
  98         };
  99
 100         spi_led_pins: spic-pins-29-to-32 {
 101                 mux {
 102                         function = "spi";
 103                         groups = "spi1_2";
 104                 };
 105         };
 106
 107         wf_2g_5g_pins: wf_2g_5g-pins {
 108                 mux {
 109                         function = "wifi";
 110                         groups = "wf_2g", "wf_5g";
 111                 };
 112                 conf {
 113                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 114                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 115                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 116                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 117                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 118                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 119                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 120                         drive-strength = <4>;
 121                 };
 122         };
 123 };
 124
 125 &spi0 {
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&spi_flash_pins>;
 128         status = "okay";
 129
 130         flash@0 {
 131                 compatible = "spi-nand";
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 reg = <0>;
 135
 136                 mediatek,nmbm;
 137                 mediatek,bmt-max-ratio = <1>;
 138                 mediatek,bmt-max-reserved-blocks = <64>;
 139
 140                 spi-max-frequency = <20000000>;
 141                 spi-tx-buswidth = <4>;
 142                 spi-rx-buswidth = <4>;
 143
 144                 partitions: partitions {
 145                         compatible = "fixed-partitions";
 146                         #address-cells = <1>;
 147                         #size-cells = <1>;
 148
 149                         partition@0 {
 150                                 label = "BL2";
 151                                 reg = <0x0 0x100000>;
 152                                 read-only;
 153                         };
 154
 155                         partition@100000 {
 156                                 label = "Nvram";
 157                                 reg = <0x100000 0x40000>;
 158                         };
 159
 160                         partition@140000 {
 161                                 label = "Bdata";
 162                                 reg = <0x140000 0x40000>;
 163                         };
 164
 165                         factory: partition@180000 {
 166                                 label = "Factory";
 167                                 reg = <0x180000 0x200000>;
 168                                 read-only;
 169
 170                                 compatible = "nvmem-cells";
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173
 174                                 macaddr_factory_4: macaddr@4 {
 175                                         reg = <0x4 0x6>;
 176                                 };
 177                         };
 178
 179                         partition@380000 {
 180                                 label = "FIP";
 181                                 reg = <0x380000 0x200000>;
 182                                 read-only;
 183                         };
 184
 185                         partition@580000 {
 186                                 label = "crash";
 187                                 reg = <0x580000 0x40000>;
 188                                 read-only;
 189                         };
 190
 191                         partition@5c0000 {
 192                                 label = "crash_log";
 193                                 reg = <0x5c0000 0x40000>;
 194                                 read-only;
 195                         };
 196                 };
 197         };
 198 };
 199
 200 &spi1 {
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&spi_led_pins>;
 203         status = "okay";
 204
 205         ws2812b@0 {
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208                 compatible = "worldsemi,ws2812b";
 209                 reg = <0>;
 210                 spi-max-frequency = <3000000>;
 211
 212                 led_status_rgb: led@0 {
 213                         reg = <0>;
 214                         label = "rgb:status";
 215                         color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 216                 };
 217
 218                 led_network_rgb: led@1 {
 219                         reg = <1>;
 220                         label = "rgb:network";
 221                         color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 222                 };
 223         };
 224 };
 225
 226 &switch {
 227         ports {
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230
 231                 port@1 {
 232                         reg = <1>;
 233                         label = "lan4";
 234                 };
 235
 236                 port@2 {
 237                         reg = <2>;
 238                         label = "lan3";
 239                 };
 240
 241                 port@3 {
 242                         reg = <3>;
 243                         label = "lan2";
 244                 };
 245
 246                 port@4 {
 247                         reg = <4>;
 248                         label = "wan";
 249                 };
 250
 251                 port@6 {
 252                         reg = <6>;
 253                         label = "cpu";
 254                         ethernet = <&gmac0>;
 255                         phy-mode = "2500base-x";
 256
 257                         fixed-link {
 258                                 speed = <2500>;
 259                                 full-duplex;
 260                                 pause;
 261                         };
 262                 };
 263         };
 264 };
 265
 266 &wmac {
 267         status = "okay";
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&wf_2g_5g_pins>;
 270
 271         mediatek,mtd-eeprom = <&factory 0x0>;
 272 };
 273
 274 &uart0 {
 275         status = "okay";
 276 };