1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include "mt7986a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
13 model = "Zyxel EX5601-T0";
14 compatible = "zyxel,ex5601-t0", "mediatek,mt7986a-rfb-snand";
21 stdout-path = "serial0:115200n8";
25 reg = <0 0x40000000 0 0x40000000>;
28 reg_1p8v: regulator-1p8v {
29 compatible = "regulator-fixed";
30 regulator-name = "fixed-1.8V";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
37 reg_3p3v: regulator-3p3v {
38 compatible = "regulator-fixed";
39 regulator-name = "fixed-3.3V";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
46 reg_5v: regulator-5v {
47 compatible = "regulator-fixed";
48 regulator-name = "fixed-5V";
49 regulator-min-microvolt = <5000000>;
50 regulator-max-microvolt = <5000000>;
56 compatible = "gpio-keys";
61 gpios = <&pio 21 GPIO_ACTIVE_LOW>;
62 linux,code = <KEY_RESTART>;
67 gpios = <&pio 11 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_WLAN>;
72 gpios = <&pio 56 GPIO_ACTIVE_LOW>;
73 linux,code = <KEY_WPS_BUTTON>;
78 compatible = "gpio-leds";
81 label = "zyled-green-wifi24g";
82 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
83 default-state = "off";
87 label = "zyled-green-wifi5g";
88 gpios = <&pio 2 GPIO_ACTIVE_LOW>;
89 default-state = "off";
93 label = "zyled-green-inet";
94 gpios = <&pio 14 GPIO_ACTIVE_LOW>;
95 default-state = "off";
99 label = "zyled-red-inet";
100 gpios = <&pio 15 GPIO_ACTIVE_LOW>;
101 default-state = "off";
105 label = "zyled-green-pwr";
106 gpios = <&pio 13 GPIO_ACTIVE_LOW>;
107 linux,default-trigger = "timer"; /* Default blinking */
108 led-pattern = <125 125>; /* Fast blink is 4 HZ */
112 label = "zyled-red-pwr";
113 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
114 default-state = "off";
118 label = "zyled-green-fxs";
119 gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
120 default-state = "off";
124 label = "zyled-amber-fxs";
125 gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
126 default-state = "off";
130 label = "zyled-amber-wps24g";
131 gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
132 default-state = "off";
136 label = "zyled-amber-wps5g";
137 gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
138 default-state = "off";
142 label = "zyled-green-lan";
143 gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
144 default-state = "off";
148 label = "zyled-green-sfp";
149 gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
150 default-state = "off";
161 compatible = "mediatek,eth-mac";
163 phy-mode = "2500base-x";
165 nvmem-cells = <&macaddr_factory_002a>;
166 nvmem-cell-names = "mac-address";
176 compatible = "mediatek,eth-mac";
178 phy-mode = "2500base-x";
181 nvmem-cells = <&macaddr_factory_0024>;
182 nvmem-cell-names = "mac-address";
186 #address-cells = <1>;
188 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
189 reset-delay-us = <1500000>;
190 reset-post-delay-us = <1000000>;
193 compatible = "ethernet-phy-ieee802.3-c45";
198 compatible = "ethernet-phy-ieee802.3-c45";
203 compatible = "mediatek,mt7531";
205 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
208 #address-cells = <1>;
229 phy-mode = "2500base-x";
236 phy-mode = "2500base-x";
255 pinctrl-names = "default", "dbdc";
256 pinctrl-0 = <&wf_2g_5g_pins>;
257 pinctrl-1 = <&wf_dbdc_pins>;
258 mediatek,mtd-eeprom = <&factory 0x0>;
259 nvmem-cells = <&macaddr_factory_0004>;
260 nvmem-cell-names = "mac-address";
268 pinctrl-names = "default", "state_uhs";
269 pinctrl-0 = <&mmc0_pins_default>;
270 pinctrl-1 = <&mmc0_pins_uhs>;
272 max-frequency = <200000000>;
276 hs400-ds-delay = <0x14014>;
277 vmmc-supply = <®_3p3v>;
278 vqmmc-supply = <®_1p8v>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&pcie_pins>;
296 mmc0_pins_default: mmc0-pins {
302 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
303 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
304 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
306 drive-strength = <4>;
307 mediatek,pull-up-adv = <1>; /* pull-up 10K */
311 drive-strength = <6>;
312 mediatek,pull-down-adv = <2>; /* pull-down 50K */
316 mediatek,pull-down-adv = <2>; /* pull-down 50K */
320 drive-strength = <4>;
321 mediatek,pull-up-adv = <1>; /* pull-up 10K */
325 mmc0_pins_uhs: mmc0-uhs-pins {
331 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
332 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
333 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
335 drive-strength = <4>;
336 mediatek,pull-up-adv = <1>; /* pull-up 10K */
340 drive-strength = <6>;
341 mediatek,pull-down-adv = <2>; /* pull-down 50K */
345 mediatek,pull-down-adv = <2>; /* pull-down 50K */
349 drive-strength = <4>;
350 mediatek,pull-up-adv = <1>; /* pull-up 10K */
354 pcie_pins: pcie-pins {
357 groups = "pcie_clk", "pcie_wake", "pcie_pereset";
361 spic_pins_g2: spic-pins-29-to-32 {
368 spi_flash_pins: spi-flash-pins-33-to-38 {
371 groups = "spi0", "spi0_wp_hold";
374 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
375 drive-strength = <8>;
376 mediatek,pull-up-adv = <0>; /* bias-disable */
379 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
380 drive-strength = <8>;
381 mediatek,pull-down-adv = <0>; /* bias-disable */
385 uart1_pins: uart1-pins {
392 uart2_pins: uart2-pins {
399 wf_2g_5g_pins: wf_2g_5g-pins {
402 groups = "wf_2g", "wf_5g";
405 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
406 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
407 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
408 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
409 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
410 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
411 "WF1_TOP_CLK", "WF1_TOP_DATA";
412 drive-strength = <4>;
416 wf_dbdc_pins: wf_dbdc-pins {
422 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
423 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
424 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
425 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
426 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
427 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
428 "WF1_TOP_CLK", "WF1_TOP_DATA";
429 drive-strength = <4>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&spi_flash_pins>;
438 #address-cells = <1>;
442 spi_nand: spi_nand@0 {
443 #address-cells = <1>;
445 compatible = "spi-nand";
447 spi-max-frequency = <10000000>;
448 spi-tx-bus-width = <4>;
449 spi-rx-bus-width = <4>;
452 compatible = "fixed-partitions";
453 #address-cells = <1>;
458 reg = <0x00000 0x0100000>;
463 label = "u-boot-env";
464 reg = <0x0100000 0x0080000>;
467 factory: partition@180000 {
469 reg = <0x180000 0x0200000>;
475 reg = <0x380000 0x01C0000>;
481 reg = <0x540000 0x0040000>;
487 reg = <0x580000 0x4000000>;
492 reg = <0x4580000 0x4000000>;
498 reg = <0x8580000 0x15A80000>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&spic_pins_g2>;
509 proslic_spi: proslic_spi@0 {
510 compatible = "silabs,proslic_spi";
512 spi-max-frequency = <10000000>;
516 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
517 reset_gpio = <&pio 7 GPIO_ACTIVE_HIGH>;
518 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
523 vusb33-supply = <®_3p3v>;
524 vbus-supply = <®_5v>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&uart1_pins>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&uart2_pins>;
553 compatible = "nvmem-cells";
554 #address-cells = <1>;
557 macaddr_factory_0004: macaddr@0004 {
561 macaddr_factory_0024: macaddr@0024 {
565 macaddr_factory_002a: macaddr@002a {