1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
8 #include "mt7986b.dtsi"
11 #address-cells = <0x2>;
13 model = "Netgear WAX220";
14 compatible = "netgear,wax220", "mediatek,mt7986b-spim-snand-rfb";
18 led-boot = &led_power_blue;
19 led-failsafe = &led_power_amber;
20 led-running = &led_power_green;
21 led-upgrade = &led_power_amber;
25 compatible = "gpio-keys";
28 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
29 linux,code = <KEY_RESTART>;
35 stdout-path = "serial0:115200n8";
39 compatible = "gpio-leds";
42 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
43 label = "green:wlan5g";
46 led_power_amber: power_amber {
47 gpios = <&pio 15 GPIO_ACTIVE_LOW>;
48 label = "amber:power";
52 gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
53 label = "green:wlan2g";
56 led_power_blue: power_blue {
57 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
61 led_power_green: power_green {
62 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
63 label = "green:power";
67 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
68 label = "blue:wlan2g";
72 gpios = <&pio 22 GPIO_ACTIVE_HIGH>;
77 gpios = <&pio 13 GPIO_ACTIVE_LOW>;
82 gpios = <&pio 2 GPIO_ACTIVE_LOW>;
83 label = "blue:wlan5g";
96 compatible = "mediatek,eth-mac";
99 phy-mode = "2500base-x";
103 #address-cells = <1>;
109 #address-cells = <1>;
111 phy6: ethernet-phy@6 {
113 reset-assert-us = <100000>;
114 reset-deassert-us = <100000>;
115 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
116 interrupt-controller;
117 #interrupt-cells = <1>;
118 interrupt-parent = <&pio>;
119 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
125 spi_flash_pins: spi-flash-pins-33-to-38 {
128 groups = "spi0", "spi0_wp_hold";
131 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
132 drive-strength = <8>;
133 mediatek,pull-up-adv = <0>; /* bias-disable */
136 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
137 drive-strength = <8>;
138 mediatek,pull-down-adv = <0>; /* bias-disable */
142 wf_2g_5g_pins: wf_2g_5g-pins {
145 groups = "wf_2g", "wf_5g";
148 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
149 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
150 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
151 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
152 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
153 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
154 "WF1_TOP_CLK", "WF1_TOP_DATA";
155 drive-strength = <4>;
159 wf_dbdc_pins: wf-dbdc-pins {
165 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
166 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
167 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
168 "WF0_TOP_CLK", "WF0_TOP_DATA";
169 drive-strength = <4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&spi_flash_pins>;
179 spi_nand_flash: flash@0 {
180 #address-cells = <1>;
182 compatible = "spi-nand";
185 spi-max-frequency = <20000000>;
186 spi-tx-buswidth = <4>;
187 spi-rx-buswidth = <4>;
189 partitions: partitions {
190 #address-cells = <0x1>;
192 compatible = "fixed-partitions";
196 reg = <0x5fc0000 0x200000>;
200 label = "NTGRcryptD";
201 reg = <0x63c0000 0x500000>;
206 reg = <0x580000 0x5140000>;
209 factory: partition@180000 {
211 reg = <0x180000 0x200000>;
216 reg = <0x69c0000 0x640000>;
220 label = "u-boot-env";
221 reg = <0x100000 0x80000>;
226 reg = <0x68c0000 0x100000>;
231 reg = <0x5ac0000 0x100000>;
237 reg = <0x0 0x100000>;
242 reg = <0x5bc0000 0x400000>;
247 reg = <0x61c0000 0x100000>;
252 reg = <0x380000 0x200000>;
257 reg = <0x56c0000 0x400000>;
261 label = "NTGRcryptK";
262 reg = <0x62c0000 0x100000>;
283 pinctrl-names = "default", "dbdc";
284 pinctrl-0 = <&wf_2g_5g_pins>;
285 pinctrl-1 = <&wf_dbdc_pins>;
287 mediatek,mtd-eeprom = <&factory 0x0>;