2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: John Crispin <blogic@openwrt.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/clock/mt2701-clk.h>
18 #include <dt-bindings/power/mt2701-power.h>
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/reset/mt2701-resets.h>
21 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
22 #include "skeleton64.dtsi"
26 compatible = "mediatek,mt7623";
27 interrupt-parent = <&sysirq>;
32 enable-method = "mediatek,mt6589-smp";
36 compatible = "arm,cortex-a7";
38 clocks = <&infracfg CLK_INFRA_CPUSEL>,
39 <&apmixedsys CLK_APMIXED_MAINPLL>;
40 clock-names = "cpu", "intermediate";
51 compatible = "arm,cortex-a7";
53 clocks = <&infracfg CLK_INFRA_CPUSEL>,
54 <&apmixedsys CLK_APMIXED_MAINPLL>;
55 clock-names = "cpu", "intermediate";
66 compatible = "arm,cortex-a7";
68 clocks = <&infracfg CLK_INFRA_CPUSEL>,
69 <&apmixedsys CLK_APMIXED_MAINPLL>;
70 clock-names = "cpu", "intermediate";
81 compatible = "arm,cortex-a7";
83 clocks = <&infracfg CLK_INFRA_CPUSEL>,
84 <&apmixedsys CLK_APMIXED_MAINPLL>;
85 clock-names = "cpu", "intermediate";
96 system_clk: dummy13m {
97 compatible = "fixed-clock";
98 clock-frequency = <13000000>;
103 compatible = "fixed-clock";
104 clock-frequency = <32000>;
106 clock-output-names = "clk32k";
110 compatible = "fixed-clock";
111 clock-frequency = <26000000>;
113 clock-output-names = "clk26m";
117 compatible = "arm,armv7-timer";
118 interrupt-parent = <&gic>;
119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
123 clock-frequency = <13000000>;
124 arm,cpu-registers-not-fw-configured;
127 topckgen: power-controller@10000000 {
128 compatible = "mediatek,mt7623-topckgen",
129 "mediatek,mt2701-topckgen",
131 reg = <0 0x10000000 0 0x1000>;
135 infracfg: power-controller@10001000 {
136 compatible = "mediatek,mt7623-infracfg",
137 "mediatek,mt2701-infracfg",
139 reg = <0 0x10001000 0 0x1000>;
144 pericfg: pericfg@10003000 {
145 compatible = "mediatek,mt7623-pericfg",
146 "mediatek,mt2701-pericfg",
148 reg = <0 0x10003000 0 0x1000>;
153 pio: pinctrl@10005000 {
154 compatible = "mediatek,mt7623-pinctrl";
155 reg = <0 0x1000b000 0 0x1000>;
156 mediatek,pctl-regmap = <&syscfg_pctl_a>;
160 interrupt-controller;
161 interrupt-parent = <&gic>;
162 #interrupt-cells = <2>;
163 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
167 syscfg_pctl_a: syscfg@10005000 {
168 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
169 reg = <0 0x10005000 0 0x1000>;
172 scpsys: scpsys@10006000 {
173 #power-domain-cells = <1>;
174 compatible = "mediatek,mt7623-scpsys",
175 "mediatek,mt2701-scpsys";
176 reg = <0 0x10006000 0 0x1000>;
177 infracfg = <&infracfg>;
179 <&topckgen CLK_TOP_MM_SEL>;
180 clock-names = "mfg", "mm";
183 watchdog: watchdog@10007000 {
184 compatible = "mediatek,mt7623-wdt",
185 "mediatek,mt6589-wdt";
186 reg = <0 0x10007000 0 0x100>;
189 timer: timer@10008000 {
190 compatible = "mediatek,mt7623-timer",
191 "mediatek,mt6577-timer";
192 reg = <0 0x10008000 0 0x80>;
193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
194 clocks = <&system_clk>, <&rtc_clk>;
195 clock-names = "system-clk", "rtc-clk";
198 pwrap: pwrap@1000d000 {
199 compatible = "mediatek,mt7623-pwrap",
200 "mediatek,mt2701-pwrap";
201 reg = <0 0x1000d000 0 0x1000>;
203 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
204 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
205 reset-names = "pwrap";
206 clocks = <&infracfg CLK_INFRA_PMICSPI>,
207 <&infracfg CLK_INFRA_PMICWRAP>;
208 clock-names = "spi", "wrap";
211 sysirq: interrupt-controller@10200100 {
212 compatible = "mediatek,mt7623-sysirq",
213 "mediatek,mt6577-sysirq";
214 interrupt-controller;
215 #interrupt-cells = <3>;
216 interrupt-parent = <&gic>;
217 reg = <0 0x10200100 0 0x1c>;
220 apmixedsys: apmixedsys@10209000 {
221 compatible = "mediatek,mt7623-apmixedsys",
222 "mediatek,mt2701-apmixedsys";
223 reg = <0 0x10209000 0 0x1000>;
227 gic: interrupt-controller@10211000 {
228 compatible = "arm,cortex-a7-gic";
229 interrupt-controller;
230 #interrupt-cells = <3>;
231 interrupt-parent = <&gic>;
232 reg = <0 0x10211000 0 0x1000>,
233 <0 0x10212000 0 0x1000>,
234 <0 0x10214000 0 0x2000>,
235 <0 0x10216000 0 0x2000>;
239 compatible = "mediatek,mt7623-i2c",
240 "mediatek,mt6577-i2c";
241 reg = <0 0x11007000 0 0x70>,
242 <0 0x11000200 0 0x80>;
243 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
245 clocks = <&pericfg CLK_PERI_I2C0>,
246 <&pericfg CLK_PERI_AP_DMA>;
247 clock-names = "main", "dma";
248 #address-cells = <1>;
254 compatible = "mediatek,mt7623-i2c",
255 "mediatek,mt6577-i2c";
256 reg = <0 0x11008000 0 0x70>,
257 <0 0x11000280 0 0x80>;
258 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
260 clocks = <&pericfg CLK_PERI_I2C1>,
261 <&pericfg CLK_PERI_AP_DMA>;
262 clock-names = "main", "dma";
263 #address-cells = <1>;
269 compatible = "mediatek,mt7623-i2c",
270 "mediatek,mt6577-i2c";
271 reg = <0 0x11009000 0 0x70>,
272 <0 0x11000300 0 0x80>;
273 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
275 clocks = <&pericfg CLK_PERI_I2C2>,
276 <&pericfg CLK_PERI_AP_DMA>;
277 clock-names = "main", "dma";
278 #address-cells = <1>;
283 uart0: serial@11002000 {
284 compatible = "mediatek,mt7623-uart",
285 "mediatek,mt6577-uart";
286 reg = <0 0x11002000 0 0x400>;
287 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
288 clocks = <&pericfg CLK_PERI_UART0_SEL>,
289 <&pericfg CLK_PERI_UART0>;
290 clock-names = "baud", "bus";
294 uart1: serial@11003000 {
295 compatible = "mediatek,mt7623-uart",
296 "mediatek,mt6577-uart";
297 reg = <0 0x11003000 0 0x400>;
298 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
299 clocks = <&pericfg CLK_PERI_UART1_SEL>,
300 <&pericfg CLK_PERI_UART1>;
301 clock-names = "baud", "bus";
305 uart2: serial@11004000 {
306 compatible = "mediatek,mt7623-uart",
307 "mediatek,mt6577-uart";
308 reg = <0 0x11004000 0 0x400>;
309 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
310 clocks = <&pericfg CLK_PERI_UART2_SEL>,
311 <&pericfg CLK_PERI_UART2>;
312 clock-names = "baud", "bus";
316 uart3: serial@11005000 {
317 compatible = "mediatek,mt7623-uart",
318 "mediatek,mt6577-uart";
319 reg = <0 0x11005000 0 0x400>;
320 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
321 clocks = <&pericfg CLK_PERI_UART3_SEL>,
322 <&pericfg CLK_PERI_UART3>;
323 clock-names = "baud", "bus";
328 compatible = "mediatek,mt7623-pwm";
330 reg = <0 0x11006000 0 0x1000>;
332 resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
336 clocks = <&topckgen CLK_TOP_PWM_SEL>,
337 <&pericfg CLK_PERI_PWM>,
338 <&pericfg CLK_PERI_PWM1>,
339 <&pericfg CLK_PERI_PWM2>,
340 <&pericfg CLK_PERI_PWM3>,
341 <&pericfg CLK_PERI_PWM4>,
342 <&pericfg CLK_PERI_PWM5>;
343 clock-names = "top", "main", "pwm1", "pwm2",
344 "pwm3", "pwm4", "pwm5";
350 compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
351 reg = <0 0x1100a000 0 0x1000>;
352 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
353 clocks = <&pericfg CLK_PERI_SPI0>;
354 clock-names = "main";
359 nandc: nfi@1100d000 {
360 compatible = "mediatek,mt2701-nfc";
361 reg = <0 0x1100d000 0 0x1000>;
362 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
363 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
364 clocks = <&pericfg CLK_PERI_NFI>,
365 <&pericfg CLK_PERI_NFI_PAD>;
366 clock-names = "nfi_clk", "pad_clk";
369 #address-cells = <1>;
374 compatible = "mediatek,mt2701-ecc";
375 reg = <0 0x1100e000 0 0x1000>;
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
377 clocks = <&pericfg CLK_PERI_NFI_ECC>;
378 clock-names = "nfiecc_clk";
383 compatible = "mediatek,mt7623-mmc",
384 "mediatek,mt8135-mmc";
385 reg = <0 0x11230000 0 0x1000>;
386 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
387 clocks = <&pericfg CLK_PERI_MSDC30_0>,
388 <&topckgen CLK_TOP_MSDC30_0_SEL>;
389 clock-names = "source", "hclk";
394 compatible = "mediatek,mt7623-mmc",
395 "mediatek,mt8135-mmc";
396 reg = <0 0x11240000 0 0x1000>;
397 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
398 clocks = <&pericfg CLK_PERI_MSDC30_1>,
399 <&topckgen CLK_TOP_MSDC30_1_SEL>;
400 clock-names = "source", "hclk";
405 compatible = "mediatek,mt2701-xhci",
406 "mediatek,mt8173-xhci";
407 reg = <0 0x1a1c0000 0 0x1000>,
408 <0 0x1a1c4700 0 0x0100>;
409 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
410 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
411 <&topckgen CLK_TOP_ETHIF_SEL>;
412 clock-names = "sys_ck", "ethif";
413 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
414 phys = <&phy_port0 PHY_TYPE_USB3>;
418 u3phy1: usb-phy@1a1c4000 {
419 compatible = "mediatek,mt2701-u3phy",
420 "mediatek,mt8173-u3phy";
421 reg = <0 0x1a1c4000 0 0x0700>;
423 clock-names = "u3phya_ref";
425 #address-cells = <2>;
430 phy_port0: phy_port0: port@1a1c4800 {
431 reg = <0 0x1a1c4800 0 0x800>;
438 compatible = "mediatek,mt2701-xhci",
439 "mediatek,mt8173-xhci";
440 reg = <0 0x1a240000 0 0x1000>,
441 <0 0x1a244700 0 0x0100>;
442 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
443 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
444 <&topckgen CLK_TOP_ETHIF_SEL>;
445 clock-names = "sys_ck", "ethif";
446 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
451 u3phy2: usb-phy@1a244000 {
452 compatible = "mediatek,mt2701-u3phy",
453 "mediatek,mt8173-u3phy";
454 reg = <0 0x1a244000 0 0x0700>,
455 <0 0x1a244800 0 0x0800>;
457 clock-names = "u3phya_ref";
462 hifsys: clock-controller@1a000000 {
463 compatible = "mediatek,mt7623-hifsys",
464 "mediatek,mt2701-hifsys",
466 reg = <0 0x1a000000 0 0x1000>;
471 pcie: pcie@1a140000 {
472 compatible = "mediatek,mt7623-pcie";
474 reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
475 <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
476 <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
477 <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
478 reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
479 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
480 <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
481 <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
482 interrupt-names = "pcie0", "pcie1", "pcie2";
483 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
484 clock-names = "pcie";
485 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
486 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
487 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
488 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
489 reset-names = "pcie0", "pcie1", "pcie2";
491 mediatek,hifsys = <&hifsys>;
493 bus-range = <0x00 0xff>;
494 #address-cells = <3>;
497 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
498 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
504 reg = <0x0800 0 0 0 0>;
506 #address-cells = <3>;
513 reg = <0x1000 0 0 0 0>;
515 #address-cells = <3>;
522 reg = <0x1800 0 0 0 0>;
524 #address-cells = <3>;
530 ethsys: syscon@1b000000 {
531 compatible = "mediatek,mt2701-ethsys", "syscon";
532 reg = <0 0x1b000000 0 0x1000>;
537 eth: ethernet@1b100000 {
538 compatible = "mediatek,mt2701-eth";
539 reg = <0 0x1b100000 0 0x20000>;
541 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
542 <ðsys CLK_ETHSYS_ESW>,
543 <ðsys CLK_ETHSYS_GP2>,
544 <ðsys CLK_ETHSYS_GP1>;
545 clock-names = "ethif", "esw", "gp2", "gp1";
546 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
547 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
548 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
549 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
551 resets = <ðsys 6>;
554 mediatek,ethsys = <ðsys>;
555 mediatek,pctl = <&syscfg_pctl_a>;
557 mediatek,switch = <&gsw>;
559 #address-cells = <1>;
565 compatible = "mediatek,eth-mac";
580 compatible = "mediatek,eth-mac";
587 #address-cells = <1>;
590 phy5: ethernet-phy@5 {
592 phy-mode = "rgmii-rxid";
595 phy1f: ethernet-phy@1f {
602 gsw: switch@1b100000 {
603 compatible = "mediatek,mt7623-gsw";
604 interrupt-parent = <&pio>;
605 interrupts = <168 IRQ_TYPE_EDGE_RISING>;
606 resets = <ðsys 2>;
608 clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
609 clock-names = "trgpll";
610 mt7530-supply = <&mt6323_vpa_reg>;
611 mediatek,pctl-regmap = <&syscfg_pctl_a>;
612 mediatek,ethsys = <ðsys>;