2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: John Crispin <blogic@openwrt.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/clock/mt2701-clk.h>
18 #include <dt-bindings/power/mt2701-power.h>
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/reset/mt2701-resets.h>
21 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
22 #include <dt-bindings/gpio/gpio.h>
23 #include "skeleton64.dtsi"
27 compatible = "mediatek,mt7623";
28 interrupt-parent = <&sysirq>;
33 enable-method = "mediatek,mt6589-smp";
37 compatible = "arm,cortex-a7";
39 clocks = <&infracfg CLK_INFRA_CPUSEL>,
40 <&apmixedsys CLK_APMIXED_MAINPLL>;
41 clock-names = "cpu", "intermediate";
52 compatible = "arm,cortex-a7";
54 clocks = <&infracfg CLK_INFRA_CPUSEL>,
55 <&apmixedsys CLK_APMIXED_MAINPLL>;
56 clock-names = "cpu", "intermediate";
67 compatible = "arm,cortex-a7";
69 clocks = <&infracfg CLK_INFRA_CPUSEL>,
70 <&apmixedsys CLK_APMIXED_MAINPLL>;
71 clock-names = "cpu", "intermediate";
82 compatible = "arm,cortex-a7";
84 clocks = <&infracfg CLK_INFRA_CPUSEL>,
85 <&apmixedsys CLK_APMIXED_MAINPLL>;
86 clock-names = "cpu", "intermediate";
97 system_clk: dummy13m {
98 compatible = "fixed-clock";
99 clock-frequency = <13000000>;
104 compatible = "fixed-clock";
105 clock-frequency = <32000>;
107 clock-output-names = "clk32k";
111 compatible = "fixed-clock";
112 clock-frequency = <26000000>;
114 clock-output-names = "clk26m";
118 compatible = "arm,armv7-timer";
119 interrupt-parent = <&gic>;
120 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
123 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
124 clock-frequency = <13000000>;
125 arm,cpu-registers-not-fw-configured;
128 topckgen: power-controller@10000000 {
129 compatible = "mediatek,mt7623-topckgen",
130 "mediatek,mt2701-topckgen",
132 reg = <0 0x10000000 0 0x1000>;
136 infracfg: power-controller@10001000 {
137 compatible = "mediatek,mt7623-infracfg",
138 "mediatek,mt2701-infracfg",
140 reg = <0 0x10001000 0 0x1000>;
145 pericfg: pericfg@10003000 {
146 compatible = "mediatek,mt7623-pericfg",
147 "mediatek,mt2701-pericfg",
149 reg = <0 0x10003000 0 0x1000>;
154 pio: pinctrl@10005000 {
155 compatible = "mediatek,mt7623-pinctrl";
156 reg = <0 0x1000b000 0 0x1000>;
157 mediatek,pctl-regmap = <&syscfg_pctl_a>;
161 interrupt-controller;
162 interrupt-parent = <&gic>;
163 #interrupt-cells = <2>;
164 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
168 syscfg_pctl_a: syscfg@10005000 {
169 compatible = "mediatek,mt7623-pctl-a-syscfg",
170 "mediatek,mt2701-pctl-a-syscfg",
172 reg = <0 0x10005000 0 0x1000>;
175 scpsys: scpsys@10006000 {
176 #power-domain-cells = <1>;
177 compatible = "mediatek,mt7623-scpsys",
178 "mediatek,mt2701-scpsys";
179 reg = <0 0x10006000 0 0x1000>;
180 infracfg = <&infracfg>;
182 <&topckgen CLK_TOP_MM_SEL>,
183 <&topckgen CLK_TOP_ETHIF_SEL>;
184 clock-names = "mfg", "mm", "ethif";
187 watchdog: watchdog@10007000 {
188 compatible = "mediatek,mt7623-wdt",
189 "mediatek,mt6589-wdt";
190 reg = <0 0x10007000 0 0x100>;
193 timer: timer@10008000 {
194 compatible = "mediatek,mt7623-timer",
195 "mediatek,mt6577-timer";
196 reg = <0 0x10008000 0 0x80>;
197 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
198 clocks = <&system_clk>, <&rtc_clk>;
199 clock-names = "system-clk", "rtc-clk";
202 pwrap: pwrap@1000d000 {
203 compatible = "mediatek,mt7623-pwrap",
204 "mediatek,mt2701-pwrap";
205 reg = <0 0x1000d000 0 0x1000>;
207 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
208 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
209 reset-names = "pwrap";
210 clocks = <&infracfg CLK_INFRA_PMICSPI>,
211 <&infracfg CLK_INFRA_PMICWRAP>;
212 clock-names = "spi", "wrap";
216 compatible = "mediatek,mt7623-cir";
217 reg = <0 0x10013000 0 0x1000>;
218 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
219 clocks = <&infracfg CLK_INFRA_IRRX>;
224 sysirq: interrupt-controller@10200100 {
225 compatible = "mediatek,mt7623-sysirq",
226 "mediatek,mt6577-sysirq";
227 interrupt-controller;
228 #interrupt-cells = <3>;
229 interrupt-parent = <&gic>;
230 reg = <0 0x10200100 0 0x1c>;
233 efuse: efuse@10206000 {
234 compatible = "mediatek,mt7623-efuse",
236 reg = <0 0x10206000 0 0x1000>;
237 #address-cells = <1>;
241 thermal_calibration: calib@424 {
246 apmixedsys: apmixedsys@10209000 {
247 compatible = "mediatek,mt7623-apmixedsys",
248 "mediatek,mt2701-apmixedsys";
249 reg = <0 0x10209000 0 0x1000>;
254 compatible = "mediatek,mt7623-rng";
255 reg = <0 0x1020f000 0 0x1000>;
256 clocks = <&infracfg CLK_INFRA_TRNG>;
260 gic: interrupt-controller@10211000 {
261 compatible = "arm,cortex-a7-gic";
262 interrupt-controller;
263 #interrupt-cells = <3>;
264 interrupt-parent = <&gic>;
265 reg = <0 0x10211000 0 0x1000>,
266 <0 0x10212000 0 0x1000>,
267 <0 0x10214000 0 0x2000>,
268 <0 0x10216000 0 0x2000>;
271 auxadc: adc@11001000 {
272 compatible = "mediatek,mt7623-auxadc",
273 "mediatek,mt2701-auxadc";
274 reg = <0 0x11001000 0 0x1000>;
275 clocks = <&pericfg CLK_PERI_AUXADC>;
276 clock-names = "main";
277 #io-channel-cells = <1>;
280 uart0: serial@11002000 {
281 compatible = "mediatek,mt7623-uart",
282 "mediatek,mt6577-uart";
283 reg = <0 0x11002000 0 0x400>;
284 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
285 clocks = <&pericfg CLK_PERI_UART0_SEL>,
286 <&pericfg CLK_PERI_UART0>;
287 clock-names = "baud", "bus";
291 uart1: serial@11003000 {
292 compatible = "mediatek,mt7623-uart",
293 "mediatek,mt6577-uart";
294 reg = <0 0x11003000 0 0x400>;
295 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
296 clocks = <&pericfg CLK_PERI_UART1_SEL>,
297 <&pericfg CLK_PERI_UART1>;
298 clock-names = "baud", "bus";
302 uart2: serial@11004000 {
303 compatible = "mediatek,mt7623-uart",
304 "mediatek,mt6577-uart";
305 reg = <0 0x11004000 0 0x400>;
306 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
307 clocks = <&pericfg CLK_PERI_UART2_SEL>,
308 <&pericfg CLK_PERI_UART2>;
309 clock-names = "baud", "bus";
313 uart3: serial@11005000 {
314 compatible = "mediatek,mt7623-uart",
315 "mediatek,mt6577-uart";
316 reg = <0 0x11005000 0 0x400>;
317 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
318 clocks = <&pericfg CLK_PERI_UART3_SEL>,
319 <&pericfg CLK_PERI_UART3>;
320 clock-names = "baud", "bus";
325 compatible = "mediatek,mt7623-pwm";
327 reg = <0 0x11006000 0 0x1000>;
328 resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
332 clocks = <&topckgen CLK_TOP_PWM_SEL>,
333 <&pericfg CLK_PERI_PWM>,
334 <&pericfg CLK_PERI_PWM1>,
335 <&pericfg CLK_PERI_PWM2>,
336 <&pericfg CLK_PERI_PWM3>,
337 <&pericfg CLK_PERI_PWM4>,
338 <&pericfg CLK_PERI_PWM5>;
339 clock-names = "top", "main", "pwm1", "pwm2",
340 "pwm3", "pwm4", "pwm5";
346 compatible = "mediatek,mt7623-i2c",
347 "mediatek,mt6577-i2c";
348 reg = <0 0x11007000 0 0x70>,
349 <0 0x11000200 0 0x80>;
350 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
352 clocks = <&pericfg CLK_PERI_I2C0>,
353 <&pericfg CLK_PERI_AP_DMA>;
354 clock-names = "main", "dma";
355 #address-cells = <1>;
361 compatible = "mediatek,mt7623-i2c",
362 "mediatek,mt6577-i2c";
363 reg = <0 0x11008000 0 0x70>,
364 <0 0x11000280 0 0x80>;
365 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
367 clocks = <&pericfg CLK_PERI_I2C1>,
368 <&pericfg CLK_PERI_AP_DMA>;
369 clock-names = "main", "dma";
370 #address-cells = <1>;
376 compatible = "mediatek,mt7623-i2c",
377 "mediatek,mt6577-i2c";
378 reg = <0 0x11009000 0 0x70>,
379 <0 0x11000300 0 0x80>;
380 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
382 clocks = <&pericfg CLK_PERI_I2C2>,
383 <&pericfg CLK_PERI_AP_DMA>;
384 clock-names = "main", "dma";
385 #address-cells = <1>;
391 compatible = "mediatek,mt7623-spi",
392 "mediatek,mt6589-spi";
393 reg = <0 0x1100a000 0 0x1000>;
394 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
395 clocks = <&pericfg CLK_PERI_SPI0>;
396 clock-names = "main";
401 thermal: thermal@1100b000 {
402 #thermal-sensor-cells = <1>;
403 compatible = "mediatek,mt2701-thermal",
404 "mediatek,mt2701-thermal";
405 reg = <0 0x1100b000 0 0x1000>;
406 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
407 clocks = <&pericfg CLK_PERI_THERM>,
408 <&pericfg CLK_PERI_AUXADC>;
409 clock-names = "therm", "auxadc";
410 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
411 reset-names = "therm";
412 mediatek,auxadc = <&auxadc>;
413 mediatek,apmixedsys = <&apmixedsys>;
415 nvmem-cells = <&thermal_calibration>;
416 nvmem-cell-names = "calibration-data";
420 compatible = "mediatek,mt7623-spi",
421 "mediatek,mt2701-spi";
422 #address-cells = <1>;
424 reg = <0 0x11016000 0 0x100>;
425 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
426 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
427 <&topckgen CLK_TOP_SPI1_SEL>,
428 <&pericfg CLK_PERI_SPI1>;
429 clock-names = "parent-clk", "sel-clk", "spi-clk";
434 compatible = "mediatek,mt7623-spi",
435 "mediatek,mt2701-spi";
436 #address-cells = <1>;
438 reg = <0 0x11017000 0 0x1000>;
439 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
440 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
441 <&topckgen CLK_TOP_SPI2_SEL>,
442 <&pericfg CLK_PERI_SPI2>;
443 clock-names = "parent-clk", "sel-clk", "spi-clk";
447 nandc: nfi@1100d000 {
448 compatible = "mediatek,mt7623-nfc",
449 "mediatek,mt2701-nfc";
450 reg = <0 0x1100d000 0 0x1000>;
451 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
452 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
453 clocks = <&pericfg CLK_PERI_NFI>,
454 <&pericfg CLK_PERI_NFI_PAD>;
455 clock-names = "nfi_clk", "pad_clk";
458 #address-cells = <1>;
463 compatible = "mediatek,mt7623-ecc",
464 "mediatek,mt2701-ecc";
465 reg = <0 0x1100e000 0 0x1000>;
466 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
467 clocks = <&pericfg CLK_PERI_NFI_ECC>;
468 clock-names = "nfiecc_clk";
472 afe: audio-controller@11220000 {
473 compatible = "mediatek,mt7623-audio",
474 "mediatek,mt2701-audio";
475 reg = <0 0x11220000 0 0x2000>,
476 <0 0x112a0000 0 0x20000>;
477 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
478 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
480 clocks = <&infracfg CLK_INFRA_AUDIO>,
481 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
482 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
483 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
484 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
485 <&topckgen CLK_TOP_AUD_48K_TIMING>,
486 <&topckgen CLK_TOP_AUD_44K_TIMING>,
487 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
488 <&topckgen CLK_TOP_APLL_SEL>,
489 <&topckgen CLK_TOP_AUD1PLL_98M>,
490 <&topckgen CLK_TOP_AUD2PLL_90M>,
491 <&topckgen CLK_TOP_HADDS2PLL_98M>,
492 <&topckgen CLK_TOP_HADDS2PLL_294M>,
493 <&topckgen CLK_TOP_AUDPLL>,
494 <&topckgen CLK_TOP_AUDPLL_D4>,
495 <&topckgen CLK_TOP_AUDPLL_D8>,
496 <&topckgen CLK_TOP_AUDPLL_D16>,
497 <&topckgen CLK_TOP_AUDPLL_D24>,
498 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
500 <&topckgen CLK_TOP_SYSPLL1_D4>,
501 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
502 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
503 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
504 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
505 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
506 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
507 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
508 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
509 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
510 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
511 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
512 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
513 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
514 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
515 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
516 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
517 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
518 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
519 <&topckgen CLK_TOP_ASM_M_SEL>,
520 <&topckgen CLK_TOP_ASM_H_SEL>,
521 <&topckgen CLK_TOP_UNIVPLL2_D4>,
522 <&topckgen CLK_TOP_UNIVPLL2_D2>,
523 <&topckgen CLK_TOP_SYSPLL_D5>;
524 clock-names = "infra_sys_audio_clk",
525 "top_audio_mux1_sel",
526 "top_audio_mux2_sel",
527 "top_audio_mux1_div",
528 "top_audio_mux2_div",
529 "top_audio_48k_timing",
530 "top_audio_44k_timing",
531 "top_audpll_mux_sel",
535 "top_hadds2_pll_98M",
536 "top_hadds2_pll_294M",
545 "top_aud_k1_src_sel",
546 "top_aud_k2_src_sel",
547 "top_aud_k3_src_sel",
548 "top_aud_k4_src_sel",
549 "top_aud_k5_src_sel",
550 "top_aud_k6_src_sel",
551 "top_aud_k1_src_div",
552 "top_aud_k2_src_div",
553 "top_aud_k3_src_div",
554 "top_aud_k4_src_div",
555 "top_aud_k5_src_div",
556 "top_aud_k6_src_div",
571 compatible = "mediatek,mt7623-mmc",
572 "mediatek,mt8135-mmc";
573 reg = <0 0x11230000 0 0x1000>;
574 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
575 clocks = <&pericfg CLK_PERI_MSDC30_0>,
576 <&topckgen CLK_TOP_MSDC30_0_SEL>;
577 clock-names = "source", "hclk";
582 compatible = "mediatek,mt7623-mmc",
583 "mediatek,mt8135-mmc";
584 reg = <0 0x11240000 0 0x1000>;
585 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
586 clocks = <&pericfg CLK_PERI_MSDC30_1>,
587 <&topckgen CLK_TOP_MSDC30_1_SEL>;
588 clock-names = "source", "hclk";
593 compatible = "mediatek,mt7623-xhci",
594 "mediatek,mt8173-xhci";
595 reg = <0 0x1a1c0000 0 0x1000>,
596 <0 0x1a1c4700 0 0x0100>;
597 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
598 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
599 <&topckgen CLK_TOP_ETHIF_SEL>;
600 clock-names = "sys_ck", "ethif";
601 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
602 phys = <&phy_port0 PHY_TYPE_USB3>;
606 u3phy1: usb-phy@1a1c4000 {
607 compatible = "mediatek,mt2701-u3phy",
608 "mediatek,mt8173-u3phy";
609 reg = <0 0x1a1c4000 0 0x0700>;
611 clock-names = "u3phya_ref";
613 #address-cells = <2>;
618 phy_port0: phy_port0: port@1a1c4800 {
619 reg = <0 0x1a1c4800 0 0x800>;
626 compatible = "mediatek,mt2701-xhci",
627 "mediatek,mt8173-xhci";
628 reg = <0 0x1a240000 0 0x1000>,
629 <0 0x1a244700 0 0x0100>;
630 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
631 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
632 <&topckgen CLK_TOP_ETHIF_SEL>;
633 clock-names = "sys_ck", "ethif";
634 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
639 u3phy2: usb-phy@1a244000 {
640 compatible = "mediatek,mt2701-u3phy",
641 "mediatek,mt8173-u3phy";
642 reg = <0 0x1a244000 0 0x0700>,
643 <0 0x1a244800 0 0x0800>;
645 clock-names = "u3phya_ref";
650 hifsys: clock-controller@1a000000 {
651 compatible = "mediatek,mt7623-hifsys",
652 "mediatek,mt2701-hifsys",
654 reg = <0 0x1a000000 0 0x1000>;
659 pcie: pcie@1a140000 {
660 compatible = "mediatek,mt7623-pcie";
662 reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
663 <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
664 <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
665 <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
666 reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
667 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
668 <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
669 <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
670 interrupt-names = "pcie0", "pcie1", "pcie2";
671 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
672 clock-names = "pcie";
673 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
674 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
675 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
676 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
677 reset-names = "pcie0", "pcie1", "pcie2";
679 mediatek,hifsys = <&hifsys>;
681 bus-range = <0x00 0xff>;
682 #address-cells = <3>;
685 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
686 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
692 reg = <0x0800 0 0 0 0>;
694 #address-cells = <3>;
701 reg = <0x1000 0 0 0 0>;
703 #address-cells = <3>;
710 reg = <0x1800 0 0 0 0>;
712 #address-cells = <3>;
718 ethsys: syscon@1b000000 {
719 compatible = "mediatek,mt7623-ethsys",
720 "mediatek,mt2701-ethsys",
722 reg = <0 0x1b000000 0 0x1000>;
727 eth: ethernet@1b100000 {
728 compatible = "mediatek,mt7623-eth",
729 "mediatek,mt2701-eth",
731 reg = <0 0x1b100000 0 0x20000>;
733 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
734 <ðsys CLK_ETHSYS_ESW>,
735 <ðsys CLK_ETHSYS_GP2>,
736 <ðsys CLK_ETHSYS_GP1>,
737 <&apmixedsys CLK_APMIXED_TRGPLL>;
738 clock-names = "ethif", "esw", "gp2", "gp1", "trgpll";
739 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
740 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
741 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
742 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
744 resets = <ðsys 6>;
747 mediatek,ethsys = <ðsys>;
748 mediatek,pctl = <&syscfg_pctl_a>;
750 #address-cells = <1>;
756 compatible = "mediatek,eth-mac";
771 compatible = "mediatek,eth-mac";
778 #address-cells = <1>;
783 hnat: hnat@1b000000 {
784 compatible = "mediatek,mt7623-hnat";
785 reg = <0 0x1b100000 0 0x3000>;
787 resets = <ðsys 0>;
788 reset-names = "mtketh";
791 crypto: crypto@1b240000 {
792 compatible = "mediatek,mt7623-crypto", "mediatek,eip97-crypto";
793 reg = <0 0x1b240000 0 0x20000>;
794 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
795 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
796 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
797 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
798 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
799 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
800 <ðsys CLK_ETHSYS_CRYPTO>;
801 clock-names = "ethif","cryp";
802 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;