2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
12 #include "mt7622.dtsi"
13 #include "mt6380.dtsi"
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
24 stdout-path = "serial0:115200n8";
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
36 sram-supply = <&mt6380_vm_reg>;
41 compatible = "gpio-keys";
46 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
51 linux,code = <KEY_WPS_BUTTON>;
52 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
57 compatible = "gpio-leds";
60 label = "bpi-r64:pio:green";
61 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
62 default-state = "off";
66 label = "bpi-r64:pio:red";
67 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
68 default-state = "off";
73 compatible = "mediatek,mt753x";
74 mediatek,ethsys = <ðsys>;
80 reg = <0 0x40000000 0 0x40000000>;
83 reg_1p8v: regulator-1p8v {
84 compatible = "regulator-fixed";
85 regulator-name = "fixed-1.8V";
86 regulator-min-microvolt = <1800000>;
87 regulator-max-microvolt = <1800000>;
91 reg_3p3v: regulator-3p3v {
92 compatible = "regulator-fixed";
93 regulator-name = "fixed-3.3V";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
100 reg_5v: regulator-5v {
101 compatible = "regulator-fixed";
102 regulator-name = "fixed-5V";
103 regulator-min-microvolt = <5000000>;
104 regulator-max-microvolt = <5000000>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&irrx_pins>;
125 pinctrl-names = "default";
126 pinctrl-0 = <ð_pins>;
130 compatible = "mediatek,eth-mac";
132 phy-handle = <&phy5>;
136 #address-cells = <1>;
139 phy5: ethernet-phy@5 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&i2c1_pins>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&i2c2_pins>;
159 pinctrl-names = "default", "state_uhs";
160 pinctrl-0 = <&emmc_pins_default>;
161 pinctrl-1 = <&emmc_pins_uhs>;
164 max-frequency = <50000000>;
167 vmmc-supply = <®_3p3v>;
168 vqmmc-supply = <®_1p8v>;
169 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
170 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
175 pinctrl-names = "default", "state_uhs";
176 pinctrl-0 = <&sd0_pins_default>;
177 pinctrl-1 = <&sd0_pins_uhs>;
180 max-frequency = <50000000>;
183 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
184 vmmc-supply = <®_3p3v>;
185 vqmmc-supply = <®_3p3v>;
186 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
187 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
191 pinctrl-names = "default";
192 pinctrl-0 = <¶llel_nand_pins>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&spi_nor_pins>;
202 compatible = "jedec,spi-nor";
208 pinctrl-names = "default";
209 pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
222 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
223 * SATA functions. i.e. output-high: PCIe, output-low: SATA
227 gpios = <90 GPIO_ACTIVE_HIGH>;
231 /* eMMC is shared pin with parallel NAND */
232 emmc_pins_default: emmc-pins-default {
234 function = "emmc", "emmc_rst";
238 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
239 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
240 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
243 pins = "NDL0", "NDL1", "NDL2",
244 "NDL3", "NDL4", "NDL5",
245 "NDL6", "NDL7", "NRB";
256 emmc_pins_uhs: emmc-pins-uhs {
263 pins = "NDL0", "NDL1", "NDL2",
264 "NDL3", "NDL4", "NDL5",
265 "NDL6", "NDL7", "NRB";
267 drive-strength = <4>;
273 drive-strength = <4>;
281 groups = "mdc_mdio", "rgmii_via_gmac2";
285 i2c1_pins: i2c1-pins {
292 i2c2_pins: i2c2-pins {
299 i2s1_pins: i2s1-pins {
302 groups = "i2s_out_mclk_bclk_ws",
308 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
309 "I2S_WS", "I2S_MCLK";
310 drive-strength = <12>;
315 irrx_pins: irrx-pins {
322 irtx_pins: irtx-pins {
329 /* Parallel nand is shared pin with eMMC */
330 parallel_nand_pins: parallel-nand-pins {
337 pcie0_pins: pcie0-pins {
340 groups = "pcie0_pad_perst",
346 pcie1_pins: pcie1-pins {
349 groups = "pcie1_pad_perst",
355 pmic_bus_pins: pmic-bus-pins {
362 pwm7_pins: pwm1-2-pins {
365 groups = "pwm_ch7_2";
369 wled_pins: wled-pins {
376 sd0_pins_default: sd0-pins-default {
382 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
383 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
384 * DAT2, DAT3, CMD, CLK for SD respectively.
387 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
388 "I2S2_IN","I2S4_OUT";
390 drive-strength = <8>;
395 drive-strength = <12>;
404 sd0_pins_uhs: sd0-pins-uhs {
411 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
412 "I2S2_IN","I2S4_OUT";
423 /* Serial NAND is shared pin with SPI-NOR */
424 serial_nand_pins: serial-nand-pins {
431 spic0_pins: spic0-pins {
438 spic1_pins: spic1-pins {
445 /* SPI-NOR is shared pin with serial NAND */
446 spi_nor_pins: spi-nor-pins {
453 /* serial NAND is shared pin with SPI-NOR */
454 serial_nand_pins: serial-nand-pins {
461 uart0_pins: uart0-pins {
464 groups = "uart0_0_tx_rx" ;
468 uart2_pins: uart2-pins {
471 groups = "uart2_1_tx_rx" ;
475 watchdog_pins: watchdog-pins {
477 function = "watchdog";
484 pinctrl-names = "default";
485 pinctrl-0 = <&pwm7_pins>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pmic_bus_pins>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&spic0_pins>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&spic1_pins>;
517 vusb33-supply = <®_3p3v>;
518 vbus-supply = <®_5v>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&uart0_pins>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&uart2_pins>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&watchdog_pins>;
545 mediatek,mdio = <&mdio>;
546 mediatek,portmap = "llllw";
547 mediatek,mdio_master_pinmux = <0>;
548 reset-gpios = <&pio 54 0>;
549 interrupt-parent = <&pio>;
550 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
554 compatible = "mediatek,mt753x-port";
564 compatible = "mediatek,mt753x-port";