2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "MediaTek MT7622 RFB1 board";
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
26 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
42 compatible = "gpio-keys";
43 poll-interval = <100>;
53 linux,code = <KEY_WPS_BUTTON>;
59 compatible = "mediatek,mt753x";
60 mediatek,ethsys = <ðsys>;
66 reg = <0 0x40000000 0 0x3F000000>;
69 reg_1p8v: regulator-1p8v {
70 compatible = "regulator-fixed";
71 regulator-name = "fixed-1.8V";
72 regulator-min-microvolt = <1800000>;
73 regulator-max-microvolt = <1800000>;
77 reg_3p3v: regulator-3p3v {
78 compatible = "regulator-fixed";
79 regulator-name = "fixed-3.3V";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
86 reg_5v: regulator-5v {
87 compatible = "regulator-fixed";
88 regulator-name = "fixed-5V";
89 regulator-min-microvolt = <5000000>;
90 regulator-max-microvolt = <5000000>;
97 pinctrl-names = "default", "pcie1_pins";
98 pinctrl-0 = <&pcie0_pins>;
99 pinctrl-1 = <&pcie1_pins>;
113 /* eMMC is shared pin with parallel NAND */
114 emmc_pins_default: emmc-pins-default {
116 function = "emmc", "emmc_rst";
120 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
121 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
122 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
125 pins = "NDL0", "NDL1", "NDL2",
126 "NDL3", "NDL4", "NDL5",
127 "NDL6", "NDL7", "NRB";
138 emmc_pins_uhs: emmc-pins-uhs {
145 pins = "NDL0", "NDL1", "NDL2",
146 "NDL3", "NDL4", "NDL5",
147 "NDL6", "NDL7", "NRB";
149 drive-strength = <4>;
155 drive-strength = <4>;
163 groups = "mdc_mdio", "rgmii_via_gmac2";
167 i2c1_pins: i2c1-pins {
174 i2c2_pins: i2c2-pins {
181 i2s1_pins: i2s1-pins {
184 groups = "i2s_out_mclk_bclk_ws",
190 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
191 "I2S_WS", "I2S_MCLK";
192 drive-strength = <12>;
197 irrx_pins: irrx-pins {
204 irtx_pins: irtx-pins {
211 /* Parallel nand is shared pin with eMMC */
212 parallel_nand_pins: parallel-nand-pins {
219 pcie0_pins: pcie0-pins {
222 groups = "pcie0_pad_perst",
228 pcie1_pins: pcie1-pins {
231 groups = "pcie1_pad_perst",
237 pmic_bus_pins: pmic-bus-pins {
244 pwm7_pins: pwm1-2-pins {
247 groups = "pwm_ch7_2";
251 wled_pins: wled-pins {
258 sd0_pins_default: sd0-pins-default {
264 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
265 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
266 * DAT2, DAT3, CMD, CLK for SD respectively.
269 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
270 "I2S2_IN","I2S4_OUT";
272 drive-strength = <8>;
277 drive-strength = <12>;
286 sd0_pins_uhs: sd0-pins-uhs {
293 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
294 "I2S2_IN","I2S4_OUT";
305 /* Serial NAND is shared pin with SPI-NOR */
306 serial_nand_pins: serial-nand-pins {
313 spic0_pins: spic0-pins {
320 spic1_pins: spic1-pins {
327 /* SPI-NOR is shared pin with serial NAND */
328 spi_nor_pins: spi-nor-pins {
335 /* serial NAND is shared pin with SPI-NOR */
336 serial_nand_pins: serial-nand-pins {
343 uart0_pins: uart0-pins {
346 groups = "uart0_0_tx_rx" ;
350 uart2_pins: uart2-pins {
353 groups = "uart2_1_tx_rx" ;
357 watchdog_pins: watchdog-pins {
359 function = "watchdog";
374 pinctrl-names = "default";
375 pinctrl-0 = <&irrx_pins>;
382 compatible = "mediatek,eth-mac";
392 compatible = "mediatek,eth-mac";
402 #address-cells = <1>;
408 mediatek,mdio = <&mdio>;
409 mediatek,portmap = "llllw";
410 mediatek,mdio_master_pinmux = <0>;
411 reset-gpios = <&pio 54 0>;
412 interrupt-parent = <&pio>;
413 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
417 compatible = "mediatek,mt753x-port";
427 compatible = "mediatek,mt753x-port";
438 pinctrl-names = "default";
439 pinctrl-0 = <&i2c1_pins>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&i2c2_pins>;
450 pinctrl-names = "default", "state_uhs";
451 pinctrl-0 = <&emmc_pins_default>;
452 pinctrl-1 = <&emmc_pins_uhs>;
455 max-frequency = <50000000>;
458 vmmc-supply = <®_3p3v>;
459 vqmmc-supply = <®_1p8v>;
460 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
461 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
466 pinctrl-names = "default", "state_uhs";
467 pinctrl-0 = <&sd0_pins_default>;
468 pinctrl-1 = <&sd0_pins_uhs>;
471 max-frequency = <50000000>;
474 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
475 vmmc-supply = <®_3p3v>;
476 vqmmc-supply = <®_3p3v>;
477 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
478 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
482 pinctrl-names = "default";
483 pinctrl-0 = <¶llel_nand_pins>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&spi_nor_pins>;
493 compatible = "jedec,spi-nor";
499 pinctrl-names = "default";
500 pinctrl-0 = <&pwm7_pins>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&pmic_bus_pins>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&serial_nand_pins>;
517 #address-cells = <1>;
519 compatible = "spi-nand";
520 spi-max-frequency = <104000000>;
524 compatible = "fixed-partitions";
525 #address-cells = <1>;
530 reg = <0x00000 0x0080000>;
536 reg = <0x80000 0x0040000>;
542 reg = <0xc0000 0x0080000>;
548 reg = <0x140000 0x0080000>;
554 reg = <0x1c0000 0x0040000>;
560 reg = <0x200000 0x2000000>;
565 reg = <0x2200000 0x4000000>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&spic0_pins>;
578 pinctrl-names = "default";
579 pinctrl-0 = <&spic1_pins>;
584 vusb33-supply = <®_3p3v>;
585 vbus-supply = <®_5v>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&uart0_pins>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&uart2_pins>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&watchdog_pins>;