2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "MediaTek MT7622 RFB1 board";
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
26 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
42 compatible = "gpio-keys";
43 poll-interval = <100>;
53 linux,code = <KEY_WPS_BUTTON>;
59 reg = <0 0x40000000 0 0x3F000000>;
62 reg_1p8v: regulator-1p8v {
63 compatible = "regulator-fixed";
64 regulator-name = "fixed-1.8V";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed";
72 regulator-name = "fixed-3.3V";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
79 reg_5v: regulator-5v {
80 compatible = "regulator-fixed";
81 regulator-name = "fixed-5V";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
89 compatible = "mediatek,rtk-gsw";
90 mediatek,ethsys = <ðsys>;
91 mediatek,mdio = <&mdio>;
92 mediatek,reset-pin = <&pio 54 0>;
98 pinctrl-names = "default", "pcie1_pins";
99 pinctrl-0 = <&pcie0_pins>;
100 pinctrl-1 = <&pcie1_pins>;
114 /* eMMC is shared pin with parallel NAND */
115 emmc_pins_default: emmc-pins-default {
117 function = "emmc", "emmc_rst";
121 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
122 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
123 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
126 pins = "NDL0", "NDL1", "NDL2",
127 "NDL3", "NDL4", "NDL5",
128 "NDL6", "NDL7", "NRB";
139 emmc_pins_uhs: emmc-pins-uhs {
146 pins = "NDL0", "NDL1", "NDL2",
147 "NDL3", "NDL4", "NDL5",
148 "NDL6", "NDL7", "NRB";
150 drive-strength = <4>;
156 drive-strength = <4>;
164 groups = "mdc_mdio", "rgmii_via_gmac2";
168 i2c1_pins: i2c1-pins {
175 i2c2_pins: i2c2-pins {
182 i2s1_pins: i2s1-pins {
185 groups = "i2s_out_mclk_bclk_ws",
191 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
192 "I2S_WS", "I2S_MCLK";
193 drive-strength = <12>;
198 irrx_pins: irrx-pins {
205 irtx_pins: irtx-pins {
212 /* Parallel nand is shared pin with eMMC */
213 parallel_nand_pins: parallel-nand-pins {
220 pcie0_pins: pcie0-pins {
223 groups = "pcie0_pad_perst",
229 pcie1_pins: pcie1-pins {
232 groups = "pcie1_pad_perst",
238 pmic_bus_pins: pmic-bus-pins {
245 pwm7_pins: pwm1-2-pins {
248 groups = "pwm_ch7_2";
252 wled_pins: wled-pins {
259 sd0_pins_default: sd0-pins-default {
265 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
266 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
267 * DAT2, DAT3, CMD, CLK for SD respectively.
270 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
271 "I2S2_IN","I2S4_OUT";
273 drive-strength = <8>;
278 drive-strength = <12>;
287 sd0_pins_uhs: sd0-pins-uhs {
294 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
295 "I2S2_IN","I2S4_OUT";
306 /* Serial NAND is shared pin with SPI-NOR */
307 serial_nand_pins: serial-nand-pins {
314 spic0_pins: spic0-pins {
321 spic1_pins: spic1-pins {
328 /* SPI-NOR is shared pin with serial NAND */
329 spi_nor_pins: spi-nor-pins {
336 /* serial NAND is shared pin with SPI-NOR */
337 serial_nand_pins: serial-nand-pins {
344 uart0_pins: uart0-pins {
347 groups = "uart0_0_tx_rx" ;
351 uart2_pins: uart2-pins {
354 groups = "uart2_1_tx_rx" ;
358 watchdog_pins: watchdog-pins {
360 function = "watchdog";
375 pinctrl-names = "default";
376 pinctrl-0 = <&irrx_pins>;
383 compatible = "mediatek,eth-mac";
393 compatible = "mediatek,eth-mac";
403 #address-cells = <1>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c1_pins>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c2_pins>;
421 pinctrl-names = "default", "state_uhs";
422 pinctrl-0 = <&emmc_pins_default>;
423 pinctrl-1 = <&emmc_pins_uhs>;
426 max-frequency = <50000000>;
429 vmmc-supply = <®_3p3v>;
430 vqmmc-supply = <®_1p8v>;
431 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
432 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
437 pinctrl-names = "default", "state_uhs";
438 pinctrl-0 = <&sd0_pins_default>;
439 pinctrl-1 = <&sd0_pins_uhs>;
442 max-frequency = <50000000>;
445 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
446 vmmc-supply = <®_3p3v>;
447 vqmmc-supply = <®_3p3v>;
448 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
449 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
453 pinctrl-names = "default";
454 pinctrl-0 = <¶llel_nand_pins>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&spi_nor_pins>;
464 compatible = "jedec,spi-nor";
470 pinctrl-names = "default";
471 pinctrl-0 = <&pwm7_pins>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pmic_bus_pins>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&serial_nand_pins>;
488 #address-cells = <1>;
490 compatible = "spi-nand";
491 spi-max-frequency = <104000000>;
495 compatible = "fixed-partitions";
496 #address-cells = <1>;
501 reg = <0x00000 0x0080000>;
507 reg = <0x80000 0x0040000>;
511 label = "Bootloader";
512 reg = <0xc0000 0x0080000>;
517 reg = <0x140000 0x0080000>;
522 reg = <0x1c0000 0x0040000>;
527 reg = <0x200000 0x2000000>;
532 reg = <0x2200000 0x4000000>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&spic0_pins>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&spic1_pins>;
551 vusb33-supply = <®_3p3v>;
552 vbus-supply = <®_5v>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&uart0_pins>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&uart2_pins>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&watchdog_pins>;