1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Zhanguo Ju <zhanguo.ju@mediatek.com>
7 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/hrtimer.h>
12 #include "mt753x_regs.h"
14 /* MT7531 registers */
15 #define SGMII_REG_BASE 0x5000
16 #define SGMII_REG_PORT_BASE 0x1000
17 #define SGMII_REG(p, r) (SGMII_REG_BASE + \
18 (p) * SGMII_REG_PORT_BASE + (r))
19 #define PCS_CONTROL_1(p) SGMII_REG(p, 0x00)
20 #define SGMII_MODE(p) SGMII_REG(p, 0x20)
21 #define QPHY_PWR_STATE_CTRL(p) SGMII_REG(p, 0xe8)
22 #define PHYA_CTRL_SIGNAL3(p) SGMII_REG(p, 0x128)
24 /* Fields of PCS_CONTROL_1 */
25 #define SGMII_LINK_STATUS BIT(18)
26 #define SGMII_AN_ENABLE BIT(12)
27 #define SGMII_AN_RESTART BIT(9)
29 /* Fields of SGMII_MODE */
30 #define SGMII_REMOTE_FAULT_DIS BIT(8)
31 #define SGMII_IF_MODE_FORCE_DUPLEX BIT(4)
32 #define SGMII_IF_MODE_FORCE_SPEED_S 0x2
33 #define SGMII_IF_MODE_FORCE_SPEED_M 0x0c
34 #define SGMII_IF_MODE_ADVERT_AN BIT(1)
36 /* Values of SGMII_IF_MODE_FORCE_SPEED */
37 #define SGMII_IF_MODE_FORCE_SPEED_10 0
38 #define SGMII_IF_MODE_FORCE_SPEED_100 1
39 #define SGMII_IF_MODE_FORCE_SPEED_1000 2
41 /* Fields of QPHY_PWR_STATE_CTRL */
42 #define PHYA_PWD BIT(4)
44 /* Fields of PHYA_CTRL_SIGNAL3 */
45 #define RG_TPHY_SPEED_S 2
46 #define RG_TPHY_SPEED_M 0x0c
48 /* Values of RG_TPHY_SPEED */
49 #define RG_TPHY_SPEED_1000 0
50 #define RG_TPHY_SPEED_2500 1
52 /* Unique fields of (M)HWSTRAP for MT7531 */
54 #define XTAL_FSEL_M BIT(7)
56 #define CHG_STRAP BIT(8)
58 /* Efuse Register Define */
59 #define GBE_EFUSE 0x7bc8
60 #define GBE_SEL_EFUSE_EN BIT(0)
62 /* PHY ENABLE Register bitmap define */
63 #define PHY_DEV1F 0x1f
64 #define PHY_DEV1F_REG_44 0x44
65 #define PHY_DEV1F_REG_104 0x104
66 #define PHY_DEV1F_REG_10A 0x10a
67 #define PHY_DEV1F_REG_10B 0x10b
68 #define PHY_DEV1F_REG_10C 0x10c
69 #define PHY_DEV1F_REG_10D 0x10d
70 #define PHY_DEV1F_REG_268 0x268
71 #define PHY_DEV1F_REG_269 0x269
72 #define PHY_DEV1F_REG_403 0x403
74 /* Fields of PHY_DEV1F_REG_403 */
75 #define GBE_EFUSE_SETTING BIT(3)
76 #define PHY_EN_BYPASS_MODE BIT(4)
77 #define POWER_ON_OFF BIT(5)
78 #define PHY_PLL_M GENMASK(9, 8)
79 #define PHY_PLL_SEL(x) (((x) << 8) & GENMASK(9, 8))
81 /* PHY EEE Register bitmap of define */
82 #define PHY_DEV07 0x07
83 #define PHY_DEV07_REG_03C 0x3c
85 /* PHY Extend Register 0x14 bitmap of define */
86 #define PHY_EXT_REG_14 0x14
88 /* Fields of PHY_EXT_REG_14 */
89 #define PHY_EN_DOWN_SHFIT BIT(4)
91 /* PHY Extend Register 0x17 bitmap of define */
92 #define PHY_EXT_REG_17 0x17
94 /* Fields of PHY_EXT_REG_17 */
95 #define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
97 /* PHY Token Ring Register 0x10 bitmap of define */
98 #define PHY_TR_REG_10 0x10
100 /* PHY Token Ring Register 0x12 bitmap of define */
101 #define PHY_TR_REG_12 0x12
103 /* PHY DEV 0x1e Register bitmap of define */
104 #define PHY_DEV1E 0x1e
105 #define PHY_DEV1E_REG_13 0x13
106 #define PHY_DEV1E_REG_14 0x14
107 #define PHY_DEV1E_REG_41 0x41
108 #define PHY_DEV1E_REG_A6 0xa6
109 #define PHY_DEV1E_REG_0C6 0x0c6
110 #define PHY_DEV1E_REG_0FE 0x0fe
111 #define PHY_DEV1E_REG_123 0x123
112 #define PHY_DEV1E_REG_189 0x189
114 /* Fields of PHY_DEV1E_REG_0C6 */
115 #define PHY_POWER_SAVING_S 8
116 #define PHY_POWER_SAVING_M 0x300
117 #define PHY_POWER_SAVING_TX 0x0
119 /* Fields of PHY_DEV1E_REG_189 */
120 #define DESCRAMBLER_CLEAR_EN 0x1
122 /* Values of XTAL_FSEL_S */
126 #define PLLGP_EN 0x7820
127 #define EN_COREPLL BIT(2)
128 #define SW_CLKSW BIT(1)
129 #define SW_PLLGP BIT(0)
131 #define PLLGP_CR0 0x78a8
132 #define RG_COREPLL_EN BIT(22)
133 #define RG_COREPLL_POSDIV_S 23
134 #define RG_COREPLL_POSDIV_M 0x3800000
135 #define RG_COREPLL_SDM_PCW_S 1
136 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
137 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
139 /* TOP Signals Status Register */
140 #define TOP_SIG_SR 0x780c
141 #define PAD_DUAL_SGMII_EN BIT(1)
143 /* RGMII and SGMII PLL clock */
144 #define ANA_PLLGP_CR2 0x78b0
145 #define ANA_PLLGP_CR5 0x78bc
147 /* GPIO mode define */
148 #define GPIO_MODE_REGS(x) (0x7c0c + (((x) / 8) * 4))
149 #define GPIO_MODE_S 4
151 /* GPIO GROUP IOLB SMT0 Control */
152 #define SMT0_IOLB 0x7f04
153 #define SMT_IOLB_5_SMI_MDC_EN BIT(5)
155 /* Unique fields of PMCR for MT7531 */
156 #define FORCE_MODE_EEE1G BIT(25)
157 #define FORCE_MODE_EEE100 BIT(26)
158 #define FORCE_MODE_TX_FC BIT(27)
159 #define FORCE_MODE_RX_FC BIT(28)
160 #define FORCE_MODE_DPX BIT(29)
161 #define FORCE_MODE_SPD BIT(30)
162 #define FORCE_MODE_LNK BIT(31)
163 #define FORCE_MODE BIT(15)
165 #define CHIP_REV 0x781C
166 #define CHIP_NAME_S 16
167 #define CHIP_NAME_M 0xffff0000
169 #define CHIP_REV_M 0x0f
170 #define CHIP_REV_E1 0x0
172 #define CLKGEN_CTRL 0x7500
173 #define CLK_SKEW_OUT_S 8
174 #define CLK_SKEW_OUT_M 0x300
175 #define CLK_SKEW_IN_S 6
176 #define CLK_SKEW_IN_M 0xc0
177 #define RXCLK_NO_DELAY BIT(5)
178 #define TXCLK_NO_REVERSE BIT(4)
180 #define GP_MODE_M 0x06
181 #define GP_CLK_EN BIT(0)
183 /* Values of GP_MODE */
184 #define GP_MODE_RGMII 0
185 #define GP_MODE_MII 1
186 #define GP_MODE_REV_MII 2
188 /* Values of CLK_SKEW_IN */
189 #define CLK_SKEW_IN_NO_CHANGE 0
190 #define CLK_SKEW_IN_DELAY_100PPS 1
191 #define CLK_SKEW_IN_DELAY_200PPS 2
192 #define CLK_SKEW_IN_REVERSE 3
194 /* Values of CLK_SKEW_OUT */
195 #define CLK_SKEW_OUT_NO_CHANGE 0
196 #define CLK_SKEW_OUT_DELAY_100PPS 1
197 #define CLK_SKEW_OUT_DELAY_200PPS 2
198 #define CLK_SKEW_OUT_REVERSE 3
200 /* Proprietory Control Register of Internal Phy device 0x1e */
201 #define RXADC_CONTROL_3 0xc2
202 #define RXADC_LDO_CONTROL_2 0xd3
204 /* Proprietory Control Register of Internal Phy device 0x1f */
205 #define TXVLD_DA_271 0x271
206 #define TXVLD_DA_272 0x272
207 #define TXVLD_DA_273 0x273
209 /* DSP Channel and NOD_ADDR*/
211 #define DSP_NOD_ADDR 0xD
213 /* gpio pinmux pins and functions define */
214 static int gpio_int_pins
[] = {0};
215 static int gpio_int_funcs
[] = {1};
216 static int gpio_mdc_pins
[] = {11, 20};
217 static int gpio_mdc_funcs
[] = {2, 2};
218 static int gpio_mdio_pins
[] = {12, 21};
219 static int gpio_mdio_funcs
[] = {2, 2};
221 static int mt7531_set_port_sgmii_force_mode(struct gsw_mt753x
*gsw
, u32 port
,
222 struct mt753x_port_cfg
*port_cfg
)
224 u32 speed
, port_base
, val
;
228 if (port
< 5 || port
>= MT753X_NUM_PORTS
) {
229 dev_info(gsw
->dev
, "port %d is not a SGMII port\n", port
);
233 port_base
= port
- 5;
235 switch (port_cfg
->speed
) {
237 speed
= RG_TPHY_SPEED_1000
;
240 speed
= RG_TPHY_SPEED_2500
;
243 dev_info(gsw
->dev
, "invalid SGMII speed idx %d for port %d\n",
244 port_cfg
->speed
, port
);
246 speed
= RG_TPHY_SPEED_1000
;
249 /* Step 1: Speed select register setting */
250 val
= mt753x_reg_read(gsw
, PHYA_CTRL_SIGNAL3(port_base
));
251 val
&= ~RG_TPHY_SPEED_M
;
252 val
|= speed
<< RG_TPHY_SPEED_S
;
253 mt753x_reg_write(gsw
, PHYA_CTRL_SIGNAL3(port_base
), val
);
255 /* Step 2 : Disable AN */
256 val
= mt753x_reg_read(gsw
, PCS_CONTROL_1(port_base
));
257 val
&= ~SGMII_AN_ENABLE
;
258 mt753x_reg_write(gsw
, PCS_CONTROL_1(port_base
), val
);
260 /* Step 3: SGMII force mode setting */
261 val
= mt753x_reg_read(gsw
, SGMII_MODE(port_base
));
262 val
&= ~SGMII_IF_MODE_ADVERT_AN
;
263 val
&= ~SGMII_IF_MODE_FORCE_SPEED_M
;
264 val
|= SGMII_IF_MODE_FORCE_SPEED_1000
<< SGMII_IF_MODE_FORCE_SPEED_S
;
265 val
|= SGMII_IF_MODE_FORCE_DUPLEX
;
266 /* For sgmii force mode, 0 is full duplex and 1 is half duplex */
267 if (port_cfg
->duplex
)
268 val
&= ~SGMII_IF_MODE_FORCE_DUPLEX
;
270 mt753x_reg_write(gsw
, SGMII_MODE(port_base
), val
);
272 /* Step 4: XXX: Disable Link partner's AN and set force mode */
274 /* Step 5: XXX: Special setting for PHYA ==> reserved for flexible */
276 /* Step 6 : Release PHYA power down state */
277 val
= mt753x_reg_read(gsw
, QPHY_PWR_STATE_CTRL(port_base
));
279 mt753x_reg_write(gsw
, QPHY_PWR_STATE_CTRL(port_base
), val
);
281 /* Step 7 : Polling SGMII_LINK_STATUS */
282 timeout_us
= 2000000;
283 timeout
= ktime_add_us(ktime_get(), timeout_us
);
285 val
= mt753x_reg_read(gsw
, PCS_CONTROL_1(port_base
));
286 val
&= SGMII_LINK_STATUS
;
291 if (ktime_compare(ktime_get(), timeout
) > 0)
298 static int mt7531_set_port_sgmii_an_mode(struct gsw_mt753x
*gsw
, u32 port
,
299 struct mt753x_port_cfg
*port_cfg
)
301 u32 speed
, port_base
, val
;
305 if (port
< 5 || port
>= MT753X_NUM_PORTS
) {
306 dev_info(gsw
->dev
, "port %d is not a SGMII port\n", port
);
310 port_base
= port
- 5;
312 switch (port_cfg
->speed
) {
314 speed
= RG_TPHY_SPEED_1000
;
317 speed
= RG_TPHY_SPEED_2500
;
320 dev_info(gsw
->dev
, "invalid SGMII speed idx %d for port %d\n",
321 port_cfg
->speed
, port
);
323 speed
= RG_TPHY_SPEED_1000
;
326 /* Step 1: Speed select register setting */
327 val
= mt753x_reg_read(gsw
, PHYA_CTRL_SIGNAL3(port_base
));
328 val
&= ~RG_TPHY_SPEED_M
;
329 val
|= speed
<< RG_TPHY_SPEED_S
;
330 mt753x_reg_write(gsw
, PHYA_CTRL_SIGNAL3(port_base
), val
);
332 /* Step 2: Remote fault disable */
333 val
= mt753x_reg_read(gsw
, SGMII_MODE(port
));
334 val
|= SGMII_REMOTE_FAULT_DIS
;
335 mt753x_reg_write(gsw
, SGMII_MODE(port
), val
);
337 /* Step 3: Setting Link partner's AN enable = 1 */
339 /* Step 4: Setting Link partner's device ability for speed/duplex */
341 /* Step 5: AN re-start */
342 val
= mt753x_reg_read(gsw
, PCS_CONTROL_1(port
));
343 val
|= SGMII_AN_RESTART
;
344 mt753x_reg_write(gsw
, PCS_CONTROL_1(port
), val
);
346 /* Step 6: Special setting for PHYA ==> reserved for flexible */
348 /* Step 7 : Polling SGMII_LINK_STATUS */
349 timeout_us
= 2000000;
350 timeout
= ktime_add_us(ktime_get(), timeout_us
);
352 val
= mt753x_reg_read(gsw
, PCS_CONTROL_1(port_base
));
353 val
&= SGMII_LINK_STATUS
;
358 if (ktime_compare(ktime_get(), timeout
) > 0)
365 static int mt7531_set_port_rgmii(struct gsw_mt753x
*gsw
, u32 port
)
370 dev_info(gsw
->dev
, "RGMII mode is not available for port %d\n",
375 val
= mt753x_reg_read(gsw
, CLKGEN_CTRL
);
378 val
|= GP_MODE_RGMII
<< GP_MODE_S
;
379 val
|= TXCLK_NO_REVERSE
;
380 val
|= RXCLK_NO_DELAY
;
381 val
&= ~CLK_SKEW_IN_M
;
382 val
|= CLK_SKEW_IN_NO_CHANGE
<< CLK_SKEW_IN_S
;
383 val
&= ~CLK_SKEW_OUT_M
;
384 val
|= CLK_SKEW_OUT_NO_CHANGE
<< CLK_SKEW_OUT_S
;
385 mt753x_reg_write(gsw
, CLKGEN_CTRL
, val
);
390 static int mt7531_mac_port_setup(struct gsw_mt753x
*gsw
, u32 port
,
391 struct mt753x_port_cfg
*port_cfg
)
396 if (port
< 5 || port
>= MT753X_NUM_PORTS
) {
397 dev_info(gsw
->dev
, "port %d is not a MAC port\n", port
);
401 if (port_cfg
->enabled
) {
402 pmcr
= (IPG_96BIT_WITH_SHORT_IPG
<< IPG_CFG_S
) |
403 MAC_MODE
| MAC_TX_EN
| MAC_RX_EN
|
404 BKOFF_EN
| BACKPR_EN
;
406 if (port_cfg
->force_link
) {
407 /* PMCR's speed field 0x11 is reserved,
410 speed
= port_cfg
->speed
;
411 if (port_cfg
->speed
== MAC_SPD_2500
)
412 speed
= MAC_SPD_1000
;
414 pmcr
|= FORCE_MODE_LNK
| FORCE_LINK
|
415 FORCE_MODE_SPD
| FORCE_MODE_DPX
|
416 FORCE_MODE_RX_FC
| FORCE_MODE_TX_FC
|
417 FORCE_RX_FC
| FORCE_TX_FC
|
418 (speed
<< FORCE_SPD_S
);
420 if (port_cfg
->duplex
)
424 pmcr
= FORCE_MODE_LNK
;
427 switch (port_cfg
->phy_mode
) {
428 case PHY_INTERFACE_MODE_RGMII
:
429 mt7531_set_port_rgmii(gsw
, port
);
431 case PHY_INTERFACE_MODE_SGMII
:
432 if (port_cfg
->force_link
)
433 mt7531_set_port_sgmii_force_mode(gsw
, port
, port_cfg
);
435 mt7531_set_port_sgmii_an_mode(gsw
, port
, port_cfg
);
438 if (port_cfg
->enabled
)
439 dev_info(gsw
->dev
, "%s is not supported by port %d\n",
440 phy_modes(port_cfg
->phy_mode
), port
);
442 pmcr
= FORCE_MODE_LNK
;
445 mt753x_reg_write(gsw
, PMCR(port
), pmcr
);
450 static void mt7531_core_pll_setup(struct gsw_mt753x
*gsw
)
455 val
= mt753x_reg_read(gsw
, TOP_SIG_SR
);
456 if (val
& PAD_DUAL_SGMII_EN
)
459 hwstrap
= mt753x_reg_read(gsw
, HWSTRAP
);
461 switch ((hwstrap
& XTAL_FSEL_M
) >> XTAL_FSEL_S
) {
463 /* Step 1 : Disable MT7531 COREPLL */
464 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
466 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
468 /* Step 2: switch to XTAL output */
469 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
471 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
473 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
474 val
&= ~RG_COREPLL_EN
;
475 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
477 /* Step 3: disable PLLGP and enable program PLLGP */
478 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
480 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
482 /* Step 4: program COREPLL output frequency to 500MHz */
483 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
484 val
&= ~RG_COREPLL_POSDIV_M
;
485 val
|= 2 << RG_COREPLL_POSDIV_S
;
486 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
487 usleep_range(25, 35);
489 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
490 val
&= ~RG_COREPLL_SDM_PCW_M
;
491 val
|= 0x140000 << RG_COREPLL_SDM_PCW_S
;
492 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
494 /* Set feedback divide ratio update signal to high */
495 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
496 val
|= RG_COREPLL_SDM_PCW_CHG
;
497 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
498 /* Wait for at least 16 XTAL clocks */
499 usleep_range(10, 20);
501 /* Step 5: set feedback divide ratio update signal to low */
502 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
503 val
&= ~RG_COREPLL_SDM_PCW_CHG
;
504 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
506 /* Enable 325M clock for SGMII */
507 mt753x_reg_write(gsw
, ANA_PLLGP_CR5
, 0xad0000);
509 /* Enable 250SSC clock for RGMII */
510 mt753x_reg_write(gsw
, ANA_PLLGP_CR2
, 0x4f40000);
512 /* Step 6: Enable MT7531 PLL */
513 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
514 val
|= RG_COREPLL_EN
;
515 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
517 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
519 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
520 usleep_range(25, 35);
524 /* Step 1 : Disable MT7531 COREPLL */
525 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
527 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
529 /* Step 2: switch to XTAL output */
530 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
532 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
534 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
535 val
&= ~RG_COREPLL_EN
;
536 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
538 /* Step 3: disable PLLGP and enable program PLLGP */
539 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
541 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
543 /* Step 4: program COREPLL output frequency to 500MHz */
544 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
545 val
&= ~RG_COREPLL_POSDIV_M
;
546 val
|= 2 << RG_COREPLL_POSDIV_S
;
547 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
548 usleep_range(25, 35);
550 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
551 val
&= ~RG_COREPLL_SDM_PCW_M
;
552 val
|= 0x190000 << RG_COREPLL_SDM_PCW_S
;
553 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
555 /* Set feedback divide ratio update signal to high */
556 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
557 val
|= RG_COREPLL_SDM_PCW_CHG
;
558 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
559 /* Wait for at least 16 XTAL clocks */
560 usleep_range(10, 20);
562 /* Step 5: set feedback divide ratio update signal to low */
563 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
564 val
&= ~RG_COREPLL_SDM_PCW_CHG
;
565 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
567 /* Enable 325M clock for SGMII */
568 mt753x_reg_write(gsw
, ANA_PLLGP_CR5
, 0xad0000);
570 /* Enable 250SSC clock for RGMII */
571 mt753x_reg_write(gsw
, ANA_PLLGP_CR2
, 0x4f40000);
573 /* Step 6: Enable MT7531 PLL */
574 val
= mt753x_reg_read(gsw
, PLLGP_CR0
);
575 val
|= RG_COREPLL_EN
;
576 mt753x_reg_write(gsw
, PLLGP_CR0
, val
);
578 val
= mt753x_reg_read(gsw
, PLLGP_EN
);
580 mt753x_reg_write(gsw
, PLLGP_EN
, val
);
581 usleep_range(25, 35);
586 static int mt7531_internal_phy_calibration(struct gsw_mt753x
*gsw
)
591 static int mt7531_sw_detect(struct gsw_mt753x
*gsw
, struct chip_rev
*crev
)
595 rev
= mt753x_reg_read(gsw
, CHIP_REV
);
597 if (((rev
& CHIP_NAME_M
) >> CHIP_NAME_S
) == MT7531
) {
599 topsig
= mt753x_reg_read(gsw
, TOP_SIG_SR
);
601 crev
->rev
= rev
& CHIP_REV_M
;
602 crev
->name
= topsig
& PAD_DUAL_SGMII_EN
?
603 "MT7531AE" : "MT7531BE";
612 static void pinmux_set_mux_7531(struct gsw_mt753x
*gsw
, u32 pin
, u32 mode
)
616 val
= mt753x_reg_read(gsw
, GPIO_MODE_REGS(pin
));
617 val
&= ~(0xf << (pin
& 7) * GPIO_MODE_S
);
618 val
|= mode
<< (pin
& 7) * GPIO_MODE_S
;
619 mt753x_reg_write(gsw
, GPIO_MODE_REGS(pin
), val
);
622 static int mt7531_set_gpio_pinmux(struct gsw_mt753x
*gsw
)
625 struct device_node
*np
= gsw
->dev
->of_node
;
627 /* Set GPIO 0 interrupt mode */
628 pinmux_set_mux_7531(gsw
, gpio_int_pins
[0], gpio_int_funcs
[0]);
630 of_property_read_u32(np
, "mediatek,mdio_master_pinmux", &group
);
632 /* group = 0: do nothing, 1: 1st group (AE), 2: 2nd group (BE) */
633 if (group
> 0 && group
<= 2) {
635 pinmux_set_mux_7531(gsw
, gpio_mdc_pins
[group
],
636 gpio_mdc_funcs
[group
]);
637 pinmux_set_mux_7531(gsw
, gpio_mdio_pins
[group
],
638 gpio_mdio_funcs
[group
]);
644 static void mt7531_phy_pll_setup(struct gsw_mt753x
*gsw
)
649 hwstrap
= mt753x_reg_read(gsw
, HWSTRAP
);
651 switch ((hwstrap
& XTAL_FSEL_M
) >> XTAL_FSEL_S
) {
653 /* disable pll auto calibration */
654 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_104
, 0x608);
657 val
= gsw
->mmd_read(gsw
, 0, PHY_DEV1F
,
660 val
|= PHY_PLL_SEL(3);
661 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_403
, val
);
663 /* set divider ratio */
664 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
,
665 PHY_DEV1F_REG_10A
, 0x1009);
667 /* set divider ratio */
668 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_10B
, 0x7c6);
670 /* capacitance and resistance adjustment */
671 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
,
672 PHY_DEV1F_REG_10C
, 0xa8be);
676 /* disable pll auto calibration */
677 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_104
, 0x608);
680 val
= gsw
->mmd_read(gsw
, 0, PHY_DEV1F
,
683 val
|= PHY_PLL_SEL(3);
684 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_403
, val
);
686 /* set divider ratio */
687 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
,
688 PHY_DEV1F_REG_10A
, 0x1018);
690 /* set divider ratio */
691 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_10B
, 0xc676);
693 /* capacitance and resistance adjustment */
694 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
,
695 PHY_DEV1F_REG_10C
, 0xd8be);
699 /* power down pll. additional delay is not required via mdio access */
700 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_10D
, 0x10);
703 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_10D
, 0x14);
706 static void mt7531_phy_setting(struct gsw_mt753x
*gsw
)
711 /* Adjust DAC TX Delay */
712 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_44
, 0xc0);
714 for (i
= 0; i
< MT753X_NUM_PHYS
; i
++) {
716 gsw
->mmd_write(gsw
, i
, PHY_DEV07
, PHY_DEV07_REG_03C
, 0);
718 /* Enable HW auto downshift */
719 gsw
->mii_write(gsw
, i
, 0x1f, 0x1);
720 val
= gsw
->mii_read(gsw
, i
, PHY_EXT_REG_14
);
721 val
|= PHY_EN_DOWN_SHFIT
;
722 gsw
->mii_write(gsw
, i
, PHY_EXT_REG_14
, val
);
724 /* Increase SlvDPSready time */
725 gsw
->mii_write(gsw
, i
, 0x1f, 0x52b5);
726 gsw
->mii_write(gsw
, i
, PHY_TR_REG_10
, 0xafae);
727 gsw
->mii_write(gsw
, i
, PHY_TR_REG_12
, 0x2f);
728 gsw
->mii_write(gsw
, i
, PHY_TR_REG_10
, 0x8fae);
729 gsw
->mii_write(gsw
, i
, 0x1f, 0);
731 /* Adjust 100_mse_threshold */
732 gsw
->mmd_write(gsw
, i
, PHY_DEV1E
, PHY_DEV1E_REG_123
, 0xffff);
735 gsw
->mmd_write(gsw
, i
, PHY_DEV1E
, PHY_DEV1E_REG_A6
, 0x300);
737 /* PHY link down power saving enable */
738 val
= gsw
->mii_read(gsw
, i
, PHY_EXT_REG_17
);
739 val
|= PHY_LINKDOWN_POWER_SAVING_EN
;
740 gsw
->mii_write(gsw
, i
, PHY_EXT_REG_17
, val
);
742 val
= gsw
->mmd_read(gsw
, i
, PHY_DEV1E
, PHY_DEV1E_REG_0C6
);
743 val
&= ~PHY_POWER_SAVING_M
;
744 val
|= PHY_POWER_SAVING_TX
<< PHY_POWER_SAVING_S
;
745 gsw
->mmd_write(gsw
, i
, PHY_DEV1E
, PHY_DEV1E_REG_0C6
, val
);
747 /* Set TX Pair delay selection */
748 gsw
->mmd_write(gsw
, i
, PHY_DEV1E
, PHY_DEV1E_REG_13
, 0x404);
749 gsw
->mmd_write(gsw
, i
, PHY_DEV1E
, PHY_DEV1E_REG_14
, 0x404);
753 static void mt7531_adjust_line_driving(struct gsw_mt753x
*gsw
, u32 port
)
755 /* For ADC timing margin window for LDO calibration */
756 gsw
->mmd_write(gsw
, port
, PHY_DEV1E
, RXADC_LDO_CONTROL_2
, 0x2222);
758 /* Adjust AD sample timing */
759 gsw
->mmd_write(gsw
, port
, PHY_DEV1E
, RXADC_CONTROL_3
, 0x4444);
761 /* Adjust Line driver current for different mode */
762 gsw
->mmd_write(gsw
, port
, PHY_DEV1F
, TXVLD_DA_271
, 0x2ca5);
764 /* Adjust Line driver current for different mode */
765 gsw
->mmd_write(gsw
, port
, PHY_DEV1F
, TXVLD_DA_272
, 0xc6b);
767 /* Adjust Line driver amplitude for 10BT */
768 gsw
->mmd_write(gsw
, port
, PHY_DEV1F
, TXVLD_DA_273
, 0x3000);
770 /* Adjust RX Echo path filter */
771 gsw
->mmd_write(gsw
, port
, PHY_DEV1E
, PHY_DEV1E_REG_0FE
, 0x2);
773 /* Adjust RX HVGA bias current */
774 gsw
->mmd_write(gsw
, port
, PHY_DEV1E
, PHY_DEV1E_REG_41
, 0x3333);
776 /* Adjust TX class AB driver 1 */
777 gsw
->mmd_write(gsw
, port
, PHY_DEV1F
, PHY_DEV1F_REG_268
, 0x388);
779 /* Adjust TX class AB driver 2 */
780 gsw
->mmd_write(gsw
, port
, PHY_DEV1F
, PHY_DEV1F_REG_269
, 0x4448);
783 static void mt7531_eee_setting(struct gsw_mt753x
*gsw
, u32 port
)
788 /* Disable generate signal to clear the scramble_lock when lpi mode */
789 val
= gsw
->mmd_read(gsw
, port
, PHY_DEV1E
, PHY_DEV1E_REG_189
);
790 val
&= ~DESCRAMBLER_CLEAR_EN
;
791 gsw
->mmd_write(gsw
, port
, PHY_DEV1E
, PHY_DEV1E_REG_189
, val
);
794 gsw
->mii_write(gsw
, port
, 0x1f, 0x52b5);
795 gsw
->mmd_write(gsw
, port
, 0x1e, 0x2d1, 0);
796 tr_reg_control
= (1 << 15) | (0 << 13) | (DSP_CH
<< 11) |
797 (DSP_NOD_ADDR
<< 7) | (0x8 << 1);
798 gsw
->mii_write(gsw
, port
, 17, 0x1b);
799 gsw
->mii_write(gsw
, port
, 18, 0);
800 gsw
->mii_write(gsw
, port
, 16, tr_reg_control
);
801 tr_reg_control
= (1 << 15) | (0 << 13) | (DSP_CH
<< 11) |
802 (DSP_NOD_ADDR
<< 7) | (0xf << 1);
803 gsw
->mii_write(gsw
, port
, 17, 0);
804 gsw
->mii_write(gsw
, port
, 18, 0);
805 gsw
->mii_write(gsw
, port
, 16, tr_reg_control
);
807 tr_reg_control
= (1 << 15) | (0 << 13) | (DSP_CH
<< 11) |
808 (DSP_NOD_ADDR
<< 7) | (0x10 << 1);
809 gsw
->mii_write(gsw
, port
, 17, 0x500);
810 gsw
->mii_write(gsw
, port
, 18, 0);
811 gsw
->mii_write(gsw
, port
, 16, tr_reg_control
);
812 gsw
->mii_write(gsw
, port
, 0x1f, 0);
815 static int mt7531_sw_init(struct gsw_mt753x
*gsw
)
820 gsw
->phy_base
= (gsw
->smi_addr
+ 1) & MT753X_SMI_ADDR_MASK
;
822 gsw
->mii_read
= mt753x_mii_read
;
823 gsw
->mii_write
= mt753x_mii_write
;
824 gsw
->mmd_read
= mt753x_mmd_read
;
825 gsw
->mmd_write
= mt753x_mmd_write
;
827 for (i
= 0; i
< MT753X_NUM_PHYS
; i
++) {
828 val
= gsw
->mii_read(gsw
, i
, MII_BMCR
);
830 gsw
->mii_write(gsw
, i
, MII_BMCR
, val
);
833 /* Force MAC link down before reset */
834 mt753x_reg_write(gsw
, PMCR(5), FORCE_MODE_LNK
);
835 mt753x_reg_write(gsw
, PMCR(6), FORCE_MODE_LNK
);
837 /* Switch soft reset */
838 mt753x_reg_write(gsw
, SYS_CTRL
, SW_SYS_RST
| SW_REG_RST
);
839 usleep_range(10, 20);
841 /* Enable MDC input Schmitt Trigger */
842 val
= mt753x_reg_read(gsw
, SMT0_IOLB
);
843 mt753x_reg_write(gsw
, SMT0_IOLB
, val
| SMT_IOLB_5_SMI_MDC_EN
);
845 /* Set 7531 gpio pinmux */
846 mt7531_set_gpio_pinmux(gsw
);
848 /* Global mac control settings */
849 mt753x_reg_write(gsw
, GMACCR
,
850 (15 << MTCC_LMT_S
) | (11 << MAX_RX_JUMBO_S
) |
851 RX_PKT_LEN_MAX_JUMBO
);
853 mt7531_core_pll_setup(gsw
);
854 mt7531_mac_port_setup(gsw
, 5, &gsw
->port5_cfg
);
855 mt7531_mac_port_setup(gsw
, 6, &gsw
->port6_cfg
);
860 static int mt7531_sw_post_init(struct gsw_mt753x
*gsw
)
865 mt7531_phy_pll_setup(gsw
);
867 /* Internal PHYs are disabled by default. SW should enable them.
868 * Note that this may already be enabled in bootloader stage.
870 val
= gsw
->mmd_read(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_403
);
871 val
|= PHY_EN_BYPASS_MODE
;
872 val
&= ~POWER_ON_OFF
;
873 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_403
, val
);
875 mt7531_phy_setting(gsw
);
877 for (i
= 0; i
< MT753X_NUM_PHYS
; i
++) {
878 val
= gsw
->mii_read(gsw
, i
, MII_BMCR
);
879 val
&= ~BMCR_ISOLATE
;
880 gsw
->mii_write(gsw
, i
, MII_BMCR
, val
);
883 for (i
= 0; i
< MT753X_NUM_PHYS
; i
++)
884 mt7531_adjust_line_driving(gsw
, i
);
886 for (i
= 0; i
< MT753X_NUM_PHYS
; i
++)
887 mt7531_eee_setting(gsw
, i
);
889 val
= mt753x_reg_read(gsw
, CHIP_REV
);
891 if (val
== CHIP_REV_E1
) {
892 mt7531_internal_phy_calibration(gsw
);
894 val
= mt753x_reg_read(gsw
, GBE_EFUSE
);
895 if (val
& GBE_SEL_EFUSE_EN
) {
896 val
= gsw
->mmd_read(gsw
, 0, PHY_DEV1F
,
898 val
&= ~GBE_EFUSE_SETTING
;
899 gsw
->mmd_write(gsw
, 0, PHY_DEV1F
, PHY_DEV1F_REG_403
,
902 mt7531_internal_phy_calibration(gsw
);
909 struct mt753x_sw_id mt7531_id
= {
911 .detect
= mt7531_sw_detect
,
912 .init
= mt7531_sw_init
,
913 .post_init
= mt7531_sw_post_init
916 MODULE_LICENSE("GPL");
917 MODULE_AUTHOR("Zhanguo Ju <zhanguo.ju@mediatek.com>");
918 MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch");