2 * OpenWrt swconfig support for MediaTek MT753x Gigabit switch
4 * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/list.h>
13 #include <linux/if_ether.h>
14 #include <linux/skbuff.h>
15 #include <linux/netdevice.h>
16 #include <linux/netlink.h>
17 #include <linux/bitops.h>
18 #include <net/genetlink.h>
19 #include <linux/delay.h>
20 #include <linux/phy.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/lockdep.h>
24 #include <linux/workqueue.h>
25 #include <linux/of_device.h>
28 #include "mt753x_swconfig.h"
29 #include "mt753x_regs.h"
31 #define MT753X_PORT_MIB_TXB_ID 18 /* TxByte */
32 #define MT753X_PORT_MIB_RXB_ID 37 /* RxByte */
34 #define MIB_DESC(_s, _o, _n) \
41 struct mt753x_mib_desc
{
47 static const struct mt753x_mib_desc mt753x_mibs
[] = {
48 MIB_DESC(1, STATS_TDPC
, "TxDrop"),
49 MIB_DESC(1, STATS_TCRC
, "TxCRC"),
50 MIB_DESC(1, STATS_TUPC
, "TxUni"),
51 MIB_DESC(1, STATS_TMPC
, "TxMulti"),
52 MIB_DESC(1, STATS_TBPC
, "TxBroad"),
53 MIB_DESC(1, STATS_TCEC
, "TxCollision"),
54 MIB_DESC(1, STATS_TSCEC
, "TxSingleCol"),
55 MIB_DESC(1, STATS_TMCEC
, "TxMultiCol"),
56 MIB_DESC(1, STATS_TDEC
, "TxDefer"),
57 MIB_DESC(1, STATS_TLCEC
, "TxLateCol"),
58 MIB_DESC(1, STATS_TXCEC
, "TxExcCol"),
59 MIB_DESC(1, STATS_TPPC
, "TxPause"),
60 MIB_DESC(1, STATS_TL64PC
, "Tx64Byte"),
61 MIB_DESC(1, STATS_TL65PC
, "Tx65Byte"),
62 MIB_DESC(1, STATS_TL128PC
, "Tx128Byte"),
63 MIB_DESC(1, STATS_TL256PC
, "Tx256Byte"),
64 MIB_DESC(1, STATS_TL512PC
, "Tx512Byte"),
65 MIB_DESC(1, STATS_TL1024PC
, "Tx1024Byte"),
66 MIB_DESC(2, STATS_TOC
, "TxByte"),
67 MIB_DESC(1, STATS_RDPC
, "RxDrop"),
68 MIB_DESC(1, STATS_RFPC
, "RxFiltered"),
69 MIB_DESC(1, STATS_RUPC
, "RxUni"),
70 MIB_DESC(1, STATS_RMPC
, "RxMulti"),
71 MIB_DESC(1, STATS_RBPC
, "RxBroad"),
72 MIB_DESC(1, STATS_RAEPC
, "RxAlignErr"),
73 MIB_DESC(1, STATS_RCEPC
, "RxCRC"),
74 MIB_DESC(1, STATS_RUSPC
, "RxUnderSize"),
75 MIB_DESC(1, STATS_RFEPC
, "RxFragment"),
76 MIB_DESC(1, STATS_ROSPC
, "RxOverSize"),
77 MIB_DESC(1, STATS_RJEPC
, "RxJabber"),
78 MIB_DESC(1, STATS_RPPC
, "RxPause"),
79 MIB_DESC(1, STATS_RL64PC
, "Rx64Byte"),
80 MIB_DESC(1, STATS_RL65PC
, "Rx65Byte"),
81 MIB_DESC(1, STATS_RL128PC
, "Rx128Byte"),
82 MIB_DESC(1, STATS_RL256PC
, "Rx256Byte"),
83 MIB_DESC(1, STATS_RL512PC
, "Rx512Byte"),
84 MIB_DESC(1, STATS_RL1024PC
, "Rx1024Byte"),
85 MIB_DESC(2, STATS_ROC
, "RxByte"),
86 MIB_DESC(1, STATS_RDPC_CTRL
, "RxCtrlDrop"),
87 MIB_DESC(1, STATS_RDPC_ING
, "RxIngDrop"),
88 MIB_DESC(1, STATS_RDPC_ARL
, "RxARLDrop")
92 /* Global attributes. */
93 MT753X_ATTR_ENABLE_VLAN
,
96 struct mt753x_mapping
{
98 u16 pvids
[MT753X_NUM_PORTS
];
99 u8 members
[MT753X_NUM_VLANS
];
100 u8 etags
[MT753X_NUM_VLANS
];
101 u16 vids
[MT753X_NUM_VLANS
];
102 } mt753x_defaults
[] = {
105 .pvids
= { 1, 1, 1, 1, 2, 2, 1 },
106 .members
= { 0, 0x4f, 0x30 },
107 .etags
= { 0, 0, 0 },
111 .pvids
= { 2, 1, 1, 1, 1, 2, 1 },
112 .members
= { 0, 0x5e, 0x21 },
113 .etags
= { 0, 0, 0 },
117 .pvids
= { 1, 2, 1, 1, 1, 2, 1 },
118 .members
= { 0, 0x5d, 0x22 },
119 .etags
= { 0, 0, 0 },
124 struct mt753x_mapping
*mt753x_find_mapping(struct device_node
*np
)
129 if (of_property_read_string(np
, "mediatek,portmap", &map
))
132 for (i
= 0; i
< ARRAY_SIZE(mt753x_defaults
); i
++)
133 if (!strcmp(map
, mt753x_defaults
[i
].name
))
134 return &mt753x_defaults
[i
];
139 static void mt753x_apply_mapping(struct gsw_mt753x
*gsw
,
140 struct mt753x_mapping
*map
)
144 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++)
145 gsw
->port_entries
[i
].pvid
= map
->pvids
[i
];
147 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++) {
148 gsw
->vlan_entries
[i
].member
= map
->members
[i
];
149 gsw
->vlan_entries
[i
].etags
= map
->etags
[i
];
150 gsw
->vlan_entries
[i
].vid
= map
->vids
[i
];
154 static int mt753x_get_vlan_enable(struct switch_dev
*dev
,
155 const struct switch_attr
*attr
,
156 struct switch_val
*val
)
158 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
160 val
->value
.i
= gsw
->global_vlan_enable
;
165 static int mt753x_set_vlan_enable(struct switch_dev
*dev
,
166 const struct switch_attr
*attr
,
167 struct switch_val
*val
)
169 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
171 gsw
->global_vlan_enable
= val
->value
.i
!= 0;
176 static int mt753x_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
178 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
180 if (port
>= MT753X_NUM_PORTS
)
183 *val
= mt753x_reg_read(gsw
, PPBV1(port
));
184 *val
&= GRP_PORT_VID_M
;
189 static int mt753x_set_port_pvid(struct switch_dev
*dev
, int port
, int pvid
)
191 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
193 if (port
>= MT753X_NUM_PORTS
)
196 if (pvid
< MT753X_MIN_VID
|| pvid
> MT753X_MAX_VID
)
199 gsw
->port_entries
[port
].pvid
= pvid
;
204 static void mt753x_vlan_ctrl(struct gsw_mt753x
*gsw
, u32 cmd
, u32 val
)
208 mt753x_reg_write(gsw
, VTCR
,
209 VTCR_BUSY
| ((cmd
<< VTCR_FUNC_S
) & VTCR_FUNC_M
) |
212 for (i
= 0; i
< 300; i
++) {
213 u32 val
= mt753x_reg_read(gsw
, VTCR
);
215 if ((val
& VTCR_BUSY
) == 0)
218 usleep_range(1000, 1100);
222 dev_info(gsw
->dev
, "vtcr timeout\n");
225 static int mt753x_get_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
227 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
234 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT753X_NUM_VLANS
)
237 mt753x_vlan_ctrl(gsw
, VTCR_READ_VLAN_ENTRY
, val
->port_vlan
);
239 member
= mt753x_reg_read(gsw
, VAWD1
);
240 member
&= PORT_MEM_M
;
241 member
>>= PORT_MEM_S
;
243 etags
= mt753x_reg_read(gsw
, VAWD2
);
245 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++) {
246 struct switch_port
*p
;
249 if (!(member
& BIT(i
)))
252 p
= &val
->value
.ports
[val
->len
++];
255 etag
= (etags
>> PORT_ETAG_S(i
)) & PORT_ETAG_M
;
257 if (etag
== ETAG_CTRL_TAG
)
258 p
->flags
|= BIT(SWITCH_PORT_FLAG_TAGGED
);
259 else if (etag
!= ETAG_CTRL_UNTAG
)
261 "vlan egress tag control neither untag nor tag.\n");
267 static int mt753x_set_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
269 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
274 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT753X_NUM_VLANS
||
275 val
->len
> MT753X_NUM_PORTS
)
278 for (i
= 0; i
< val
->len
; i
++) {
279 struct switch_port
*p
= &val
->value
.ports
[i
];
281 if (p
->id
>= MT753X_NUM_PORTS
)
284 member
|= BIT(p
->id
);
286 if (p
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))
290 gsw
->vlan_entries
[val
->port_vlan
].member
= member
;
291 gsw
->vlan_entries
[val
->port_vlan
].etags
= etags
;
296 static int mt753x_set_vid(struct switch_dev
*dev
,
297 const struct switch_attr
*attr
,
298 struct switch_val
*val
)
300 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
304 vlan
= val
->port_vlan
;
305 vid
= (u16
)val
->value
.i
;
307 if (vlan
< 0 || vlan
>= MT753X_NUM_VLANS
)
310 if (vid
< MT753X_MIN_VID
|| vid
> MT753X_MAX_VID
)
313 gsw
->vlan_entries
[vlan
].vid
= vid
;
317 static int mt753x_get_vid(struct switch_dev
*dev
,
318 const struct switch_attr
*attr
,
319 struct switch_val
*val
)
321 val
->value
.i
= val
->port_vlan
;
325 static int mt753x_get_port_link(struct switch_dev
*dev
, int port
,
326 struct switch_port_link
*link
)
328 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
331 if (port
< 0 || port
>= MT753X_NUM_PORTS
)
334 pmsr
= mt753x_reg_read(gsw
, PMSR(port
));
336 link
->link
= pmsr
& MAC_LNK_STS
;
337 link
->duplex
= pmsr
& MAC_DPX_STS
;
338 speed
= (pmsr
& MAC_SPD_STS_M
) >> MAC_SPD_STS_S
;
342 link
->speed
= SWITCH_PORT_SPEED_10
;
345 link
->speed
= SWITCH_PORT_SPEED_100
;
348 link
->speed
= SWITCH_PORT_SPEED_1000
;
351 /* TODO: swconfig has no support for 2500 now */
352 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
359 static int mt753x_set_port_link(struct switch_dev
*dev
, int port
,
360 struct switch_port_link
*link
)
363 if (port
>= MT753X_NUM_PHYS
)
366 return switch_generic_set_link(dev
, port
, link
);
372 static u64
get_mib_counter(struct gsw_mt753x
*gsw
, int i
, int port
)
377 offset
= mt753x_mibs
[i
].offset
;
379 if (mt753x_mibs
[i
].size
== 1)
380 return mt753x_reg_read(gsw
, MIB_COUNTER_REG(port
, offset
));
383 hi
= mt753x_reg_read(gsw
, MIB_COUNTER_REG(port
, offset
+ 4));
384 lo
= mt753x_reg_read(gsw
, MIB_COUNTER_REG(port
, offset
));
385 hi2
= mt753x_reg_read(gsw
, MIB_COUNTER_REG(port
, offset
+ 4));
388 return (hi
<< 32) | lo
;
391 static int mt753x_get_port_mib(struct switch_dev
*dev
,
392 const struct switch_attr
*attr
,
393 struct switch_val
*val
)
395 static char buf
[4096];
396 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
399 if (val
->port_vlan
>= MT753X_NUM_PORTS
)
402 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
403 "Port %d MIB counters\n", val
->port_vlan
);
405 for (i
= 0; i
< ARRAY_SIZE(mt753x_mibs
); ++i
) {
408 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
409 "%-11s: ", mt753x_mibs
[i
].name
);
410 counter
= get_mib_counter(gsw
, i
, val
->port_vlan
);
411 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
420 static int mt753x_get_port_stats(struct switch_dev
*dev
, int port
,
421 struct switch_port_stats
*stats
)
423 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
425 if (port
< 0 || port
>= MT753X_NUM_PORTS
)
428 stats
->tx_bytes
= get_mib_counter(gsw
, MT753X_PORT_MIB_TXB_ID
, port
);
429 stats
->rx_bytes
= get_mib_counter(gsw
, MT753X_PORT_MIB_RXB_ID
, port
);
434 static void mt753x_port_isolation(struct gsw_mt753x
*gsw
)
438 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++)
439 mt753x_reg_write(gsw
, PCR(i
),
440 BIT(gsw
->cpu_port
) << PORT_MATRIX_S
);
442 mt753x_reg_write(gsw
, PCR(gsw
->cpu_port
), PORT_MATRIX_M
);
444 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++)
445 mt753x_reg_write(gsw
, PVC(i
),
446 (0x8100 << STAG_VPID_S
) |
447 (VA_TRANSPARENT_PORT
<< VLAN_ATTR_S
));
450 static void mt753x_write_vlan_entry(struct gsw_mt753x
*gsw
, int vlan
, u16 vid
,
456 /* vlan port membership */
458 mt753x_reg_write(gsw
, VAWD1
,
459 IVL_MAC
| VTAG_EN
| VENTRY_VALID
|
460 ((ports
<< PORT_MEM_S
) & PORT_MEM_M
));
462 mt753x_reg_write(gsw
, VAWD1
, 0);
466 for (port
= 0; port
< MT753X_NUM_PORTS
; port
++) {
467 if (etags
& BIT(port
))
468 val
|= ETAG_CTRL_TAG
<< PORT_ETAG_S(port
);
470 val
|= ETAG_CTRL_UNTAG
<< PORT_ETAG_S(port
);
472 mt753x_reg_write(gsw
, VAWD2
, val
);
474 /* write to vlan table */
475 mt753x_vlan_ctrl(gsw
, VTCR_WRITE_VLAN_ENTRY
, vid
);
478 static int mt753x_apply_config(struct switch_dev
*dev
)
480 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
485 if (!gsw
->global_vlan_enable
) {
486 mt753x_port_isolation(gsw
);
490 /* set all ports as security mode */
491 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++)
492 mt753x_reg_write(gsw
, PCR(i
),
493 PORT_MATRIX_M
| SECURITY_MODE
);
495 /* check if a port is used in tag/untag vlan egress mode */
499 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++) {
500 u8 member
= gsw
->vlan_entries
[i
].member
;
501 u8 etags
= gsw
->vlan_entries
[i
].etags
;
506 for (j
= 0; j
< MT753X_NUM_PORTS
; j
++) {
507 if (!(member
& BIT(j
)))
511 tag_ports
|= 1u << j
;
513 untag_ports
|= 1u << j
;
517 /* set all untag-only ports as transparent and the rest as user port */
518 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++) {
519 u32 pvc_mode
= 0x8100 << STAG_VPID_S
;
521 if (untag_ports
& BIT(i
) && !(tag_ports
& BIT(i
)))
522 pvc_mode
= (0x8100 << STAG_VPID_S
) |
523 (VA_TRANSPARENT_PORT
<< VLAN_ATTR_S
);
525 mt753x_reg_write(gsw
, PVC(i
), pvc_mode
);
528 /* first clear the swtich vlan table */
529 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++)
530 mt753x_write_vlan_entry(gsw
, i
, i
, 0, 0);
532 /* now program only vlans with members to avoid
533 * clobbering remapped entries in later iterations
535 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++) {
536 u16 vid
= gsw
->vlan_entries
[i
].vid
;
537 u8 member
= gsw
->vlan_entries
[i
].member
;
538 u8 etags
= gsw
->vlan_entries
[i
].etags
;
541 mt753x_write_vlan_entry(gsw
, i
, vid
, member
, etags
);
544 /* Port Default PVID */
545 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++) {
546 int vlan
= gsw
->port_entries
[i
].pvid
;
550 if (vlan
< MT753X_NUM_VLANS
&& gsw
->vlan_entries
[vlan
].member
)
551 pvid
= gsw
->vlan_entries
[vlan
].vid
;
553 val
= mt753x_reg_read(gsw
, PPBV1(i
));
554 val
&= ~GRP_PORT_VID_M
;
556 mt753x_reg_write(gsw
, PPBV1(i
), val
);
562 static int mt753x_reset_switch(struct switch_dev
*dev
)
564 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
567 memset(gsw
->port_entries
, 0, sizeof(gsw
->port_entries
));
568 memset(gsw
->vlan_entries
, 0, sizeof(gsw
->vlan_entries
));
570 /* set default vid of each vlan to the same number of vlan, so the vid
571 * won't need be set explicitly.
573 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++)
574 gsw
->vlan_entries
[i
].vid
= i
;
579 static int mt753x_phy_read16(struct switch_dev
*dev
, int addr
, u8 reg
,
582 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
584 *value
= gsw
->mii_read(gsw
, addr
, reg
);
589 static int mt753x_phy_write16(struct switch_dev
*dev
, int addr
, u8 reg
,
592 struct gsw_mt753x
*gsw
= container_of(dev
, struct gsw_mt753x
, swdev
);
594 gsw
->mii_write(gsw
, addr
, reg
, value
);
599 static const struct switch_attr mt753x_global
[] = {
601 .type
= SWITCH_TYPE_INT
,
602 .name
= "enable_vlan",
603 .description
= "VLAN mode (1:enabled)",
605 .id
= MT753X_ATTR_ENABLE_VLAN
,
606 .get
= mt753x_get_vlan_enable
,
607 .set
= mt753x_set_vlan_enable
,
611 static const struct switch_attr mt753x_port
[] = {
613 .type
= SWITCH_TYPE_STRING
,
615 .description
= "Get MIB counters for port",
616 .get
= mt753x_get_port_mib
,
621 static const struct switch_attr mt753x_vlan
[] = {
623 .type
= SWITCH_TYPE_INT
,
625 .description
= "VLAN ID (0-4094)",
626 .set
= mt753x_set_vid
,
627 .get
= mt753x_get_vid
,
632 static const struct switch_dev_ops mt753x_swdev_ops
= {
634 .attr
= mt753x_global
,
635 .n_attr
= ARRAY_SIZE(mt753x_global
),
639 .n_attr
= ARRAY_SIZE(mt753x_port
),
643 .n_attr
= ARRAY_SIZE(mt753x_vlan
),
645 .get_vlan_ports
= mt753x_get_vlan_ports
,
646 .set_vlan_ports
= mt753x_set_vlan_ports
,
647 .get_port_pvid
= mt753x_get_port_pvid
,
648 .set_port_pvid
= mt753x_set_port_pvid
,
649 .get_port_link
= mt753x_get_port_link
,
650 .set_port_link
= mt753x_set_port_link
,
651 .get_port_stats
= mt753x_get_port_stats
,
652 .apply_config
= mt753x_apply_config
,
653 .reset_switch
= mt753x_reset_switch
,
654 .phy_read16
= mt753x_phy_read16
,
655 .phy_write16
= mt753x_phy_write16
,
658 int mt753x_swconfig_init(struct gsw_mt753x
*gsw
)
660 struct device_node
*np
= gsw
->dev
->of_node
;
661 struct switch_dev
*swdev
;
662 struct mt753x_mapping
*map
;
665 if (of_property_read_u32(np
, "mediatek,cpuport", &gsw
->cpu_port
))
666 gsw
->cpu_port
= MT753X_DFL_CPU_PORT
;
670 swdev
->name
= gsw
->name
;
671 swdev
->alias
= gsw
->name
;
672 swdev
->cpu_port
= gsw
->cpu_port
;
673 swdev
->ports
= MT753X_NUM_PORTS
;
674 swdev
->vlans
= MT753X_NUM_VLANS
;
675 swdev
->ops
= &mt753x_swdev_ops
;
677 ret
= register_switch(swdev
, NULL
);
679 dev_err(gsw
->dev
, "Failed to register switch %s\n",
684 map
= mt753x_find_mapping(gsw
->dev
->of_node
);
686 mt753x_apply_mapping(gsw
, map
);
687 mt753x_apply_config(swdev
);
692 void mt753x_swconfig_destroy(struct gsw_mt753x
*gsw
)
694 unregister_switch(&gsw
->swdev
);