1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018 MediaTek Inc.
7 #include "mt753x_regs.h"
9 struct mt753x_mapping mt753x_def_mapping
[] = {
12 .pvids
= { 1, 1, 1, 1, 2, 2, 1 },
13 .members
= { 0, 0x4f, 0x30 },
18 .pvids
= { 2, 1, 1, 1, 1, 2, 1 },
19 .members
= { 0, 0x5e, 0x21 },
24 .pvids
= { 1, 2, 1, 1, 1, 2, 1 },
25 .members
= { 0, 0x5d, 0x22 },
31 void mt753x_vlan_ctrl(struct gsw_mt753x
*gsw
, u32 cmd
, u32 val
)
35 mt753x_reg_write(gsw
, VTCR
,
36 VTCR_BUSY
| ((cmd
<< VTCR_FUNC_S
) & VTCR_FUNC_M
) |
39 for (i
= 0; i
< 300; i
++) {
40 u32 val
= mt753x_reg_read(gsw
, VTCR
);
42 if ((val
& VTCR_BUSY
) == 0)
45 usleep_range(1000, 1100);
49 dev_info(gsw
->dev
, "vtcr timeout\n");
52 static void mt753x_write_vlan_entry(struct gsw_mt753x
*gsw
, int vlan
, u16 vid
,
58 /* vlan port membership */
60 mt753x_reg_write(gsw
, VAWD1
,
61 IVL_MAC
| VTAG_EN
| VENTRY_VALID
|
62 ((ports
<< PORT_MEM_S
) & PORT_MEM_M
));
64 mt753x_reg_write(gsw
, VAWD1
, 0);
68 for (port
= 0; port
< MT753X_NUM_PORTS
; port
++) {
69 if (etags
& BIT(port
))
70 val
|= ETAG_CTRL_TAG
<< PORT_ETAG_S(port
);
72 val
|= ETAG_CTRL_UNTAG
<< PORT_ETAG_S(port
);
74 mt753x_reg_write(gsw
, VAWD2
, val
);
76 /* write to vlan table */
77 mt753x_vlan_ctrl(gsw
, VTCR_WRITE_VLAN_ENTRY
, vid
);
80 void mt753x_apply_vlan_config(struct gsw_mt753x
*gsw
)
86 /* set all ports as security mode */
87 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++)
88 mt753x_reg_write(gsw
, PCR(i
),
89 PORT_MATRIX_M
| SECURITY_MODE
);
91 /* check if a port is used in tag/untag vlan egress mode */
95 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++) {
96 u8 member
= gsw
->vlan_entries
[i
].member
;
97 u8 etags
= gsw
->vlan_entries
[i
].etags
;
102 for (j
= 0; j
< MT753X_NUM_PORTS
; j
++) {
103 if (!(member
& BIT(j
)))
107 tag_ports
|= 1u << j
;
109 untag_ports
|= 1u << j
;
113 /* set all untag-only ports as transparent and the rest as user port */
114 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++) {
115 u32 pvc_mode
= 0x8100 << STAG_VPID_S
;
117 if (untag_ports
& BIT(i
) && !(tag_ports
& BIT(i
)))
118 pvc_mode
= (0x8100 << STAG_VPID_S
) |
119 (VA_TRANSPARENT_PORT
<< VLAN_ATTR_S
);
121 mt753x_reg_write(gsw
, PVC(i
), pvc_mode
);
124 /* first clear the switch vlan table */
125 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++)
126 mt753x_write_vlan_entry(gsw
, i
, i
, 0, 0);
128 /* now program only vlans with members to avoid
129 * clobbering remapped entries in later iterations
131 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++) {
132 u16 vid
= gsw
->vlan_entries
[i
].vid
;
133 u8 member
= gsw
->vlan_entries
[i
].member
;
134 u8 etags
= gsw
->vlan_entries
[i
].etags
;
137 mt753x_write_vlan_entry(gsw
, i
, vid
, member
, etags
);
140 /* Port Default PVID */
141 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++) {
142 int vlan
= gsw
->port_entries
[i
].pvid
;
146 if (vlan
< MT753X_NUM_VLANS
&& gsw
->vlan_entries
[vlan
].member
)
147 pvid
= gsw
->vlan_entries
[vlan
].vid
;
149 val
= mt753x_reg_read(gsw
, PPBV1(i
));
150 val
&= ~GRP_PORT_VID_M
;
152 mt753x_reg_write(gsw
, PPBV1(i
), val
);
156 struct mt753x_mapping
*mt753x_find_mapping(struct device_node
*np
)
161 if (of_property_read_string(np
, "mediatek,portmap", &map
))
164 for (i
= 0; i
< ARRAY_SIZE(mt753x_def_mapping
); i
++)
165 if (!strcmp(map
, mt753x_def_mapping
[i
].name
))
166 return &mt753x_def_mapping
[i
];
171 void mt753x_apply_mapping(struct gsw_mt753x
*gsw
, struct mt753x_mapping
*map
)
175 for (i
= 0; i
< MT753X_NUM_PORTS
; i
++)
176 gsw
->port_entries
[i
].pvid
= map
->pvids
[i
];
178 for (i
= 0; i
< MT753X_NUM_VLANS
; i
++) {
179 gsw
->vlan_entries
[i
].member
= map
->members
[i
];
180 gsw
->vlan_entries
[i
].etags
= map
->etags
[i
];
181 gsw
->vlan_entries
[i
].vid
= map
->vids
[i
];