1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 * Author: Jianhui Zhao <zhaojh329@gmail.com>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
12 #include <dt-bindings/reset/mt7986-resets.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include <dt-bindings/input/linux-event-codes.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mux/mux.h>
19 compatible = "mediatek,mt7981";
20 interrupt-parent = <&gic>;
30 compatible = "arm,cortex-a53";
31 enable-method = "psci";
37 compatible = "arm,cortex-a53";
38 enable-method = "psci";
44 compatible = "mediatek,mt7981-pwm";
45 reg = <0 0x10048000 0 0x1000>;
47 clocks = <&infracfg CLK_INFRA_PWM_STA>,
48 <&infracfg CLK_INFRA_PWM_HCK>,
49 <&infracfg CLK_INFRA_PWM1_CK>,
50 <&infracfg CLK_INFRA_PWM2_CK>,
51 <&infracfg CLK_INFRA_PWM3_CK>;
52 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
56 compatible = "pwm-fan";
57 /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
58 cooling-levels = <0 128 192 255>;
64 cpu_thermal: cpu-thermal {
65 polling-delay-passive = <1000>;
66 polling-delay = <1000>;
67 thermal-sensors = <&thermal 0>;
70 temperature = <125000>;
76 temperature = <120000>;
81 cpu_trip_active_high: active-high {
82 temperature = <115000>;
87 cpu_trip_active_med: active-med {
88 temperature = <85000>;
93 cpu_trip_active_low: active-low {
94 temperature = <60000>;
102 /* active: set fan to cooling level 3 */
103 cooling-device = <&fan 3 3>;
104 trip = <&cpu_trip_active_high>;
108 /* active: set fan to cooling level 2 */
109 cooling-device = <&fan 2 2>;
110 trip = <&cpu_trip_active_med>;
114 /* passive: set fan to cooling level 1 */
115 cooling-device = <&fan 1 1>;
116 trip = <&cpu_trip_active_low>;
122 thermal: thermal@1100c800 {
123 #thermal-sensor-cells = <1>;
124 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
125 reg = <0 0x1100c800 0 0x800>;
126 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&infracfg CLK_INFRA_THERM_CK>,
128 <&infracfg CLK_INFRA_ADC_26M_CK>;
129 clock-names = "therm", "auxadc";
130 mediatek,auxadc = <&auxadc>;
131 mediatek,apmixedsys = <&apmixedsys>;
132 nvmem-cells = <&thermal_calibration>;
133 nvmem-cell-names = "calibration-data";
136 auxadc: adc@1100d000 {
137 compatible = "mediatek,mt7981-auxadc",
138 "mediatek,mt7986-auxadc",
139 "mediatek,mt7622-auxadc";
140 reg = <0 0x1100d000 0 0x1000>;
141 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
142 <&infracfg CLK_INFRA_ADC_FRC_CK>;
143 clock-names = "main", "32k";
144 #io-channel-cells = <1>;
147 wdma: wdma@15104800 {
148 compatible = "mediatek,wed-wdma";
149 reg = <0 0x15104800 0 0x400>,
150 <0 0x15104c00 0 0x400>;
153 ap2woccif: ap2woccif@151a5000 {
154 compatible = "mediatek,ap2woccif";
155 reg = <0 0x151a5000 0 0x1000>,
156 <0 0x151ad000 0 0x1000>;
157 interrupt-parent = <&gic>;
158 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
163 #address-cells = <2>;
167 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
168 secmon_reserved: secmon@43000000 {
169 reg = <0 0x43000000 0 0x30000>;
173 wmcpu_emi: wmcpu-reserved@47c80000 {
174 reg = <0 0x47c80000 0 0x100000>;
178 wo_emi0: wo-emi@47d80000 {
179 reg = <0 0x47d80000 0 0x40000>;
183 wo_data: wo-data@47dc0000 {
184 reg = <0 0x47dc0000 0 0x240000>;
188 wo_ilm0: wo-ilm@151e0000 {
189 reg = <0 0x151e0000 0 0x8000>;
193 wo_dlm0: wo-dlm@151e8000 {
194 reg = <0 0x151e8000 0 0x2000>;
198 wo_boot: wo-boot@15194000 {
199 reg = <0 0x15194000 0 0x1000>;
205 compatible = "arm,psci-0.2";
210 compatible = "mediatek,mt7981-rng";
213 clk40m: oscillator@0 {
214 compatible = "fixed-clock";
216 clock-frequency = <40000000>;
217 clock-output-names = "clkxtal";
220 infracfg: infracfg@10001000 {
221 compatible = "mediatek,mt7981-infracfg", "syscon";
222 reg = <0 0x10001000 0 0x1000>;
226 topckgen: topckgen@1001B000 {
227 compatible = "mediatek,mt7981-topckgen", "syscon";
228 reg = <0 0x1001B000 0 0x1000>;
232 apmixedsys: apmixedsys@1001E000 {
233 compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
234 reg = <0 0x1001E000 0 0x1000>;
239 compatible = "arm,armv8-timer";
240 interrupt-parent = <&gic>;
241 clock-frequency = <13000000>;
242 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
243 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
244 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
245 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
249 watchdog: watchdog@1001c000 {
250 compatible = "mediatek,mt7986-wdt",
251 "mediatek,mt6589-wdt";
252 reg = <0 0x1001c000 0 0x1000>;
253 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
258 gic: interrupt-controller@c000000 {
259 compatible = "arm,gic-v3";
260 #interrupt-cells = <3>;
261 interrupt-parent = <&gic>;
262 interrupt-controller;
263 reg = <0 0x0c000000 0 0x40000>, /* GICD */
264 <0 0x0c080000 0 0x200000>; /* GICR */
266 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
269 uart0: serial@11002000 {
270 compatible = "mediatek,mt6577-uart";
271 reg = <0 0x11002000 0 0x400>;
272 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
274 <&infracfg CLK_INFRA_UART0_CK>;
275 clock-names = "baud", "bus";
276 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
277 <&infracfg CLK_INFRA_UART0_SEL>;
278 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
279 <&topckgen CLK_TOP_UART_SEL>;
280 pinctrl-0 = <&uart0_pins>;
281 pinctrl-names = "default";
285 uart1: serial@11003000 {
286 compatible = "mediatek,mt6577-uart";
287 reg = <0 0x11003000 0 0x400>;
288 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
290 <&infracfg CLK_INFRA_UART1_CK>;
291 clock-names = "baud", "bus";
292 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
293 <&infracfg CLK_INFRA_UART1_SEL>;
294 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
295 <&topckgen CLK_TOP_UART_SEL>;
299 uart2: serial@11004000 {
300 compatible = "mediatek,mt6577-uart";
301 reg = <0 0x11004000 0 0x400>;
302 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
304 <&infracfg CLK_INFRA_UART2_CK>;
305 clock-names = "baud", "bus";
306 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
307 <&infracfg CLK_INFRA_UART2_SEL>;
308 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
309 <&topckgen CLK_TOP_UART_SEL>;
314 compatible = "mediatek,mt7981-i2c";
315 reg = <0 0x11007000 0 0x1000>,
316 <0 0x10217080 0 0x80>;
317 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
320 <&infracfg CLK_INFRA_AP_DMA_CK>,
321 <&infracfg CLK_INFRA_I2C_MCK_CK>,
322 <&infracfg CLK_INFRA_I2C_PCK_CK>;
323 clock-names = "main", "dma", "mck", "pck";
324 #address-cells = <1>;
329 pcie: pcie@11280000 {
330 compatible = "mediatek,mt7981-pcie",
331 "mediatek,mt7986-pcie";
333 reg = <0 0x11280000 0 0x4000>;
334 reg-names = "pcie-mac";
335 #address-cells = <3>;
337 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
338 bus-range = <0x00 0xff>;
339 ranges = <0x82000000 0 0x20000000
340 0x0 0x20000000 0 0x10000000>;
343 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
344 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
345 <&infracfg CLK_INFRA_IPCIER_CK>,
346 <&infracfg CLK_INFRA_IPCIEB_CK>;
348 phys = <&u3port0 PHY_TYPE_PCIE>;
349 phy-names = "pcie-phy";
351 #interrupt-cells = <1>;
352 interrupt-map-mask = <0 0 0 7>;
353 interrupt-map = <0 0 0 1 &pcie_intc 0>,
354 <0 0 0 2 &pcie_intc 1>,
355 <0 0 0 3 &pcie_intc 2>,
356 <0 0 0 4 &pcie_intc 3>;
357 pcie_intc: interrupt-controller {
358 interrupt-controller;
359 #address-cells = <0>;
360 #interrupt-cells = <1>;
364 crypto: crypto@10320000 {
365 compatible = "inside-secure,safexcel-eip97";
366 reg = <0 0x10320000 0 0x40000>;
367 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-names = "ring0", "ring1", "ring2", "ring3";
372 clocks = <&topckgen CLK_TOP_EIP97B>;
373 clock-names = "top_eip97_ck";
374 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
375 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
378 pio: pinctrl@11d00000 {
379 compatible = "mediatek,mt7981-pinctrl";
380 reg = <0 0x11d00000 0 0x1000>,
381 <0 0x11c00000 0 0x1000>,
382 <0 0x11c10000 0 0x1000>,
383 <0 0x11d20000 0 0x1000>,
384 <0 0x11e00000 0 0x1000>,
385 <0 0x11e20000 0 0x1000>,
386 <0 0x11f00000 0 0x1000>,
387 <0 0x11f10000 0 0x1000>,
388 <0 0x1000b000 0 0x1000>;
389 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
390 "iocfg_rb", "iocfg_lb", "iocfg_bl",
391 "iocfg_tm", "iocfg_tl", "eint";
394 gpio-ranges = <&pio 0 0 56>;
395 interrupt-controller;
396 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-parent = <&gic>;
398 #interrupt-cells = <2>;
400 mdio_pins: mdc-mdio-pins {
403 groups = "smi_mdc_mdio";
407 uart0_pins: uart0-pins {
414 wifi_dbdc_pins: wifi-dbdc-pins {
417 groups = "wf0_mode1";
420 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
421 "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
422 "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
423 "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
424 "WF_CBA_RESETB", "WF_DIG_RESETB";
425 drive-strength = <4>;
430 ethsys: syscon@15000000 {
431 #address-cells = <1>;
433 compatible = "mediatek,mt7981-ethsys",
434 "mediatek,mt7986-ethsys",
436 reg = <0 0x15000000 0 0x1000>;
442 compatible = "mediatek,mt7981-wed",
443 "mediatek,mt7986-wed",
445 reg = <0 0x15010000 0 0x1000>;
446 interrupt-parent = <&gic>;
447 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
448 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
449 <&wo_data>, <&wo_boot>;
450 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
451 "wo-data", "wo-boot";
452 mediatek,wo-ccif = <&wo_ccif0>;
455 eth: ethernet@15100000 {
456 compatible = "mediatek,mt7981-eth";
457 reg = <0 0x15100000 0 0x80000>;
458 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <ðsys CLK_ETH_FE_EN>,
463 <ðsys CLK_ETH_GP2_EN>,
464 <ðsys CLK_ETH_GP1_EN>,
465 <ðsys CLK_ETH_WOCPU0_EN>,
466 <&sgmiisys0 CLK_SGM0_TX_EN>,
467 <&sgmiisys0 CLK_SGM0_RX_EN>,
468 <&sgmiisys0 CLK_SGM0_CK0_EN>,
469 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
470 <&sgmiisys1 CLK_SGM1_TX_EN>,
471 <&sgmiisys1 CLK_SGM1_RX_EN>,
472 <&sgmiisys1 CLK_SGM1_CK1_EN>,
473 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
474 <&topckgen CLK_TOP_SGM_REG>,
475 <&topckgen CLK_TOP_NETSYS_SEL>,
476 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
477 clock-names = "fe", "gp2", "gp1", "wocpu0",
478 "sgmii_tx250m", "sgmii_rx250m",
479 "sgmii_cdr_ref", "sgmii_cdr_fb",
480 "sgmii2_tx250m", "sgmii2_rx250m",
481 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
482 "sgmii_ck", "netsys0", "netsys1";
483 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
484 <&topckgen CLK_TOP_SGM_325M_SEL>;
485 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
486 <&topckgen CLK_TOP_CB_SGM_325M>;
487 mediatek,ethsys = <ðsys>;
488 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
489 mediatek,infracfg = <&topmisc>;
490 mediatek,wed = <&wed>;
492 #address-cells = <1>;
497 #address-cells = <1>;
500 int_gbe_phy: ethernet-phy@0 {
502 compatible = "ethernet-phy-ieee802.3-c22";
505 nvmem-cells = <&phy_calibration>;
506 nvmem-cell-names = "phy-cal-data";
511 wo_ccif0: syscon@151a5000 {
512 compatible = "mediatek,mt7986-wo-ccif", "syscon";
513 reg = <0 0x151a5000 0 0x1000>;
514 interrupt-parent = <&gic>;
515 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
518 sgmiisys0: syscon@10060000 {
519 compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
520 reg = <0 0x10060000 0 0x1000>;
525 sgmiisys1: syscon@10070000 {
526 compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
527 reg = <0 0x10070000 0 0x1000>;
531 topmisc: topmisc@11d10000 {
532 compatible = "mediatek,mt7981-topmisc", "syscon";
533 reg = <0 0x11d10000 0 0x10000>;
537 snand: snfi@11005000 {
538 compatible = "mediatek,mt7986-snand";
539 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
540 reg-names = "nfi", "ecc";
541 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
543 <&infracfg CLK_INFRA_NFI1_CK>,
544 <&infracfg CLK_INFRA_NFI_HCK_CK>;
545 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
546 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
547 <&topckgen CLK_TOP_NFI1X_SEL>;
548 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
549 <&topckgen CLK_TOP_CB_M_D8>;
550 #address-cells = <1>;
556 compatible = "mediatek,mt7986-mmc",
557 "mediatek,mt7981-mmc";
558 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
559 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
561 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
562 <&infracfg CLK_INFRA_MSDC_66M_CK>,
563 <&infracfg CLK_INFRA_MSDC_133M_CK>;
564 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
565 <&topckgen CLK_TOP_EMMC_400M_SEL>;
566 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
567 <&topckgen CLK_TOP_CB_NET2_D2>;
568 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
572 wed_pcie: wed_pcie@10003000 {
573 compatible = "mediatek,wed_pcie";
574 reg = <0 0x10003000 0 0x10>;
578 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
579 #address-cells = <1>;
581 reg = <0 0x1100a000 0 0x100>;
582 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&topckgen CLK_TOP_CB_M_D2>,
584 <&topckgen CLK_TOP_SPI_SEL>,
585 <&infracfg CLK_INFRA_SPI0_CK>,
586 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
588 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
593 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
594 #address-cells = <1>;
596 reg = <0 0x1100b000 0 0x100>;
597 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&topckgen CLK_TOP_CB_M_D2>,
599 <&topckgen CLK_TOP_SPIM_MST_SEL>,
600 <&infracfg CLK_INFRA_SPI1_CK>,
601 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
602 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
607 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
608 #address-cells = <1>;
610 reg = <0 0x11009000 0 0x100>;
611 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&topckgen CLK_TOP_CB_M_D2>,
613 <&topckgen CLK_TOP_SPI_SEL>,
614 <&infracfg CLK_INFRA_SPI2_CK>,
615 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
616 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
620 consys: consys@10000000 {
621 compatible = "mediatek,mt7981-consys";
622 reg = <0 0x10000000 0 0x8600000>;
623 memory-region = <&wmcpu_emi>;
627 compatible = "mediatek,mt7986-xhci",
629 reg = <0 0x11200000 0 0x2e00>,
630 <0 0x11203e00 0 0x0100>;
631 reg-names = "mac", "ippc";
632 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
634 <&infracfg CLK_INFRA_IUSB_CK>,
635 <&infracfg CLK_INFRA_IUSB_133_CK>,
636 <&infracfg CLK_INFRA_IUSB_66M_CK>,
637 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
638 clock-names = "sys_ck",
643 phys = <&u2port0 PHY_TYPE_USB2>,
644 <&u3port0 PHY_TYPE_USB3>;
645 vusb33-supply = <®_3p3v>;
649 usb_phy: usb-phy@11e10000 {
650 compatible = "mediatek,mt7981",
651 "mediatek,generic-tphy-v2";
652 #address-cells = <1>;
654 ranges = <0 0 0x11e10000 0x1700>;
659 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
664 u3port0: usb-phy@700 {
666 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
669 mediatek,syscon-type = <&topmisc 0x218 0>;
674 reg_3p3v: regulator-3p3v {
675 compatible = "regulator-fixed";
676 regulator-name = "fixed-3.3V";
677 regulator-min-microvolt = <3300000>;
678 regulator-max-microvolt = <3300000>;
683 efuse: efuse@11f20000 {
684 compatible = "mediatek,mt7981-efuse",
686 reg = <0 0x11f20000 0 0x1000>;
687 #address-cells = <1>;
691 thermal_calibration: thermal-calib@274 {
695 phy_calibration: phy-calib@8dc {
699 comb_rx_imp_p0: usb3-rx-imp@8c8 {
704 comb_tx_imp_p0: usb3-tx-imp@8c8 {
709 comb_intr_p0: usb3-intr@8c9 {
715 afe: audio-controller@11210000 {
716 compatible = "mediatek,mt79xx-audio";
717 reg = <0 0x11210000 0 0x9000>;
718 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
720 <&infracfg CLK_INFRA_AUD_26M_CK>,
721 <&infracfg CLK_INFRA_AUD_L_CK>,
722 <&infracfg CLK_INFRA_AUD_AUD_CK>,
723 <&infracfg CLK_INFRA_AUD_EG2_CK>,
724 <&topckgen CLK_TOP_AUD_SEL>;
725 clock-names = "aud_bus_ck",
731 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
732 <&topckgen CLK_TOP_A1SYS_SEL>,
733 <&topckgen CLK_TOP_AUD_L_SEL>,
734 <&topckgen CLK_TOP_A_TUNER_SEL>;
735 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
736 <&topckgen CLK_TOP_APLL2_D4>,
737 <&topckgen CLK_TOP_CB_APLL2_196M>,
738 <&topckgen CLK_TOP_APLL2_D4>;
743 compatible = "mediatek,mt7981-ice_debug",
744 "mediatek,mt2701-ice_debug";
745 clocks = <&infracfg CLK_INFRA_DBG_CK>;
746 clock-names = "ice_dbg";
749 wifi: wifi@18000000 {
750 compatible = "mediatek,mt7981-wmac";
751 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
752 reset-names = "consys";
753 pinctrl-0 = <&wifi_dbdc_pins>;
754 pinctrl-names = "dbdc";
755 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
756 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
757 clock-names = "mcu", "ap2conn";
758 reg = <0 0x18000000 0 0x1000000>,
759 <0 0x10003000 0 0x1000>,
760 <0 0x11d10000 0 0x1000>;
761 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
765 memory-region = <&wmcpu_emi>;