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mediatek: add missing DTS entries for WED on MT7986
[openwrt/staging/svanheule.git] / target / linux / mediatek / files-5.15 / arch / arm64 / boot / dts / mediatek / mt7986a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mt7986-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/reset/mt7986-resets.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 clk40m: oscillator@0 {
20 compatible = "fixed-clock";
21 clock-frequency = <40000000>;
22 #clock-cells = <0>;
23 clock-output-names = "clkxtal";
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 reg = <0x0>;
34 #cooling-cells = <2>;
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 reg = <0x1>;
42 #cooling-cells = <2>;
43 };
44
45 cpu2: cpu@2 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 reg = <0x2>;
50 #cooling-cells = <2>;
51 };
52
53 cpu3: cpu@3 {
54 device_type = "cpu";
55 enable-method = "psci";
56 compatible = "arm,cortex-a53";
57 reg = <0x3>;
58 #cooling-cells = <2>;
59 };
60 };
61
62 psci {
63 compatible = "arm,psci-0.2";
64 method = "smc";
65 };
66
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
70 ranges;
71
72 /* 64 KiB reserved for ramoops/pstore */
73 ramoops@42ff0000 {
74 compatible = "ramoops";
75 reg = <0 0x42ff0000 0 0x10000>;
76 record-size = <0x1000>;
77 };
78
79 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
80 secmon_reserved: secmon@43000000 {
81 reg = <0 0x43000000 0 0x30000>;
82 no-map;
83 };
84
85 wmcpu_emi: wmcpu-reserved@4fc00000 {
86 no-map;
87 reg = <0 0x4fc00000 0 0x00100000>;
88 };
89
90 wo_emi0: wo-emi@4fd00000 {
91 reg = <0 0x4fd00000 0 0x40000>;
92 no-map;
93 };
94
95 wo_emi1: wo-emi@4fd40000 {
96 reg = <0 0x4fd40000 0 0x40000>;
97 no-map;
98 };
99
100 wo_ilm0: wo-ilm@151e0000 {
101 reg = <0 0x151e0000 0 0x8000>;
102 no-map;
103 };
104
105 wo_ilm1: wo-ilm@151f0000 {
106 reg = <0 0x151f0000 0 0x8000>;
107 no-map;
108 };
109
110 wo_data: wo-data@4fd80000 {
111 reg = <0 0x4fd80000 0 0x240000>;
112 no-map;
113 };
114
115 wo_dlm0: wo-dlm@151e8000 {
116 reg = <0 0x151e8000 0 0x2000>;
117 no-map;
118 };
119
120 wo_dlm1: wo-dlm@151f8000 {
121 reg = <0 0x151f8000 0 0x2000>;
122 no-map;
123 };
124
125 wo_boot: wo-boot@15194000 {
126 reg = <0 0x15194000 0 0x1000>;
127 no-map;
128 };
129 };
130
131 timer {
132 compatible = "arm,armv8-timer";
133 interrupt-parent = <&gic>;
134 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
135 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
136 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
137 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
138 };
139
140 soc {
141 #address-cells = <2>;
142 #size-cells = <2>;
143 compatible = "simple-bus";
144 ranges;
145
146 gic: interrupt-controller@c000000 {
147 compatible = "arm,gic-v3";
148 #interrupt-cells = <3>;
149 interrupt-parent = <&gic>;
150 interrupt-controller;
151 reg = <0 0x0c000000 0 0x10000>, /* GICD */
152 <0 0x0c080000 0 0x80000>, /* GICR */
153 <0 0x0c400000 0 0x2000>, /* GICC */
154 <0 0x0c410000 0 0x1000>, /* GICH */
155 <0 0x0c420000 0 0x2000>; /* GICV */
156 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
157 };
158
159 infracfg: infracfg@10001000 {
160 compatible = "mediatek,mt7986-infracfg", "syscon";
161 reg = <0 0x10001000 0 0x1000>;
162 #clock-cells = <1>;
163 };
164
165 topckgen: topckgen@1001b000 {
166 compatible = "mediatek,mt7986-topckgen", "syscon";
167 reg = <0 0x1001B000 0 0x1000>;
168 #clock-cells = <1>;
169 };
170
171 watchdog: watchdog@1001c000 {
172 compatible = "mediatek,mt7986-wdt",
173 "mediatek,mt6589-wdt";
174 reg = <0 0x1001c000 0 0x1000>;
175 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
176 #reset-cells = <1>;
177 };
178
179 pio: pinctrl@1001f000 {
180 compatible = "mediatek,mt7986a-pinctrl";
181 reg = <0 0x1001f000 0 0x1000>,
182 <0 0x11c30000 0 0x1000>,
183 <0 0x11c40000 0 0x1000>,
184 <0 0x11e20000 0 0x1000>,
185 <0 0x11e30000 0 0x1000>,
186 <0 0x11f00000 0 0x1000>,
187 <0 0x11f10000 0 0x1000>,
188 <0 0x1000b000 0 0x1000>;
189 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
190 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
191 gpio-controller;
192 #gpio-cells = <2>;
193 gpio-ranges = <&pio 0 0 100>;
194 interrupt-controller;
195 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
196 interrupt-parent = <&gic>;
197 #interrupt-cells = <2>;
198 };
199
200 apmixedsys: apmixedsys@1001e000 {
201 compatible = "mediatek,mt7986-apmixedsys";
202 reg = <0 0x1001E000 0 0x1000>;
203 #clock-cells = <1>;
204 };
205
206 sgmiisys0: syscon@10060000 {
207 compatible = "mediatek,mt7986-sgmiisys_0",
208 "syscon";
209 reg = <0 0x10060000 0 0x1000>;
210 #clock-cells = <1>;
211 };
212
213 sgmiisys1: syscon@10070000 {
214 compatible = "mediatek,mt7986-sgmiisys_1",
215 "syscon";
216 reg = <0 0x10070000 0 0x1000>;
217 #clock-cells = <1>;
218 };
219
220 trng: trng@1020f000 {
221 compatible = "mediatek,mt7986-rng";
222 reg = <0 0x1020f000 0 0x100>;
223 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
224 clock-names = "rng";
225 status = "okay";
226 };
227
228 crypto: crypto@10320000 {
229 compatible = "inside-secure,safexcel-eip97";
230 reg = <0 0x10320000 0 0x40000>;
231 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-names = "ring0", "ring1", "ring2", "ring3";
236 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
237 clock-names = "infra_eip97_ck";
238 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
239 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
240 status = "okay";
241 };
242
243 pwm: pwm@10048000 {
244 compatible = "mediatek,mt7986-pwm";
245 reg = <0 0x10048000 0 0x1000>;
246 #clock-cells = <1>;
247 #pwm-cells = <2>;
248 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&infracfg CLK_INFRA_PWM_HCK>,
250 <&infracfg CLK_INFRA_PWM_STA>,
251 <&infracfg CLK_INFRA_PWM1_CK>,
252 <&infracfg CLK_INFRA_PWM2_CK>;
253 clock-names = "top", "main", "pwm1", "pwm2";
254 status = "disabled";
255 };
256
257 uart0: serial@11002000 {
258 compatible = "mediatek,mt7986-uart",
259 "mediatek,mt6577-uart";
260 reg = <0 0x11002000 0 0x400>;
261 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
263 <&infracfg CLK_INFRA_UART0_CK>;
264 clock-names = "baud", "bus";
265 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
266 <&infracfg CLK_INFRA_UART0_SEL>;
267 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
268 <&topckgen CLK_TOP_UART_SEL>;
269 status = "disabled";
270 };
271
272 uart1: serial@11003000 {
273 compatible = "mediatek,mt7986-uart",
274 "mediatek,mt6577-uart";
275 reg = <0 0x11003000 0 0x400>;
276 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
278 <&infracfg CLK_INFRA_UART1_CK>;
279 clock-names = "baud", "bus";
280 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
281 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
282 status = "disabled";
283 };
284
285 uart2: serial@11004000 {
286 compatible = "mediatek,mt7986-uart",
287 "mediatek,mt6577-uart";
288 reg = <0 0x11004000 0 0x400>;
289 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
291 <&infracfg CLK_INFRA_UART2_CK>;
292 clock-names = "baud", "bus";
293 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
294 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
295 status = "disabled";
296 };
297
298 i2c0: i2c@11008000 {
299 compatible = "mediatek,mt7986-i2c";
300 reg = <0 0x11008000 0 0x90>,
301 <0 0x10217080 0 0x80>;
302 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
303 clock-div = <5>;
304 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
305 <&infracfg CLK_INFRA_AP_DMA_CK>;
306 clock-names = "main", "dma";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 status = "disabled";
310 };
311
312 spi0: spi@1100a000 {
313 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
314 reg = <0 0x1100a000 0 0x100>;
315 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&topckgen CLK_TOP_MPLL_D2>,
317 <&topckgen CLK_TOP_SPI_SEL>,
318 <&infracfg CLK_INFRA_SPI0_CK>,
319 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
320 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
321 status = "disabled";
322 };
323
324 spi1: spi@1100b000 {
325 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
326 reg = <0 0x1100b000 0 0x100>;
327 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&topckgen CLK_TOP_MPLL_D2>,
329 <&topckgen CLK_TOP_SPIM_MST_SEL>,
330 <&infracfg CLK_INFRA_SPI1_CK>,
331 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
332 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
333 status = "disabled";
334 };
335
336 auxadc: adc@1100d000 {
337 compatible = "mediatek,mt7986-auxadc",
338 "mediatek,mt7622-auxadc";
339 reg = <0 0x1100d000 0 0x1000>;
340 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
341 clock-names = "main";
342 #io-channel-cells = <1>;
343 };
344
345 ssusb: usb@11200000 {
346 compatible = "mediatek,mt7986-xhci",
347 "mediatek,mtk-xhci";
348 reg = <0 0x11200000 0 0x2e00>,
349 <0 0x11203e00 0 0x0100>;
350 reg-names = "mac", "ippc";
351 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
353 <&topckgen CLK_TOP_U2U3_XHCI_SEL>,
354 <&infracfg CLK_INFRA_IUSB_CK>,
355 <&infracfg CLK_INFRA_IUSB_133_CK>,
356 <&infracfg CLK_INFRA_IUSB_66M_CK>;
357 clock-names = "sys_ck",
358 "xhci_ck",
359 "ref_ck",
360 "mcu_ck",
361 "dma_ck";
362 phys = <&u2port0 PHY_TYPE_USB2>,
363 <&u3port0 PHY_TYPE_USB3>,
364 <&u2port1 PHY_TYPE_USB2>;
365 status = "disabled";
366 };
367
368 mmc0: mmc@11230000 {
369 compatible = "mediatek,mt7986-mmc";
370 reg = <0 0x11230000 0 0x1000>,
371 <0 0x11c20000 0 0x1000>;
372 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
374 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
375 <&infracfg CLK_INFRA_MSDC_66M_CK>,
376 <&infracfg CLK_INFRA_MSDC_133M_CK>;
377 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
378 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
379 <&topckgen CLK_TOP_EMMC_250M_SEL>;
380 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
381 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
382 status = "disabled";
383 };
384
385 thermal: thermal@1100c800 {
386 #thermal-sensor-cells = <1>;
387 compatible = "mediatek,mt7986-thermal";
388 reg = <0 0x1100c800 0 0x800>;
389 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&infracfg CLK_INFRA_THERM_CK>,
391 <&infracfg CLK_INFRA_ADC_26M_CK>;
392 clock-names = "therm", "auxadc";
393 mediatek,auxadc = <&auxadc>;
394 mediatek,apmixedsys = <&apmixedsys>;
395 nvmem-cells = <&thermal_calibration>;
396 nvmem-cell-names = "calibration-data";
397 };
398
399 pcie: pcie@11280000 {
400 compatible = "mediatek,mt7986-pcie",
401 "mediatek,mt8192-pcie";
402 device_type = "pci";
403 #address-cells = <3>;
404 #size-cells = <2>;
405 reg = <0x00 0x11280000 0x00 0x4000>;
406 reg-names = "pcie-mac";
407 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
408 bus-range = <0x00 0xff>;
409 ranges = <0x82000000 0x00 0x20000000 0x00
410 0x20000000 0x00 0x10000000>;
411 clocks = <&infracfg CLK_INFRA_PCIE_SEL>,
412 <&infracfg CLK_INFRA_IPCIE_CK>,
413 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
414 <&infracfg CLK_INFRA_IPCIER_CK>,
415 <&infracfg CLK_INFRA_IPCIEB_CK>;
416 status = "disabled";
417
418 phys = <&pcie_port PHY_TYPE_PCIE>;
419 phy-names = "pcie-phy";
420
421 #interrupt-cells = <1>;
422 interrupt-map-mask = <0 0 0 0x7>;
423 interrupt-map = <0 0 0 1 &pcie_intc 0>,
424 <0 0 0 2 &pcie_intc 1>,
425 <0 0 0 3 &pcie_intc 2>,
426 <0 0 0 4 &pcie_intc 3>;
427 pcie_intc: interrupt-controller {
428 #address-cells = <0>;
429 #interrupt-cells = <1>;
430 interrupt-controller;
431 };
432 };
433
434 pcie_phy: t-phy@11c00000 {
435 compatible = "mediatek,mt7986-tphy",
436 "mediatek,generic-tphy-v4";
437 #address-cells = <2>;
438 #size-cells = <2>;
439 ranges;
440 status = "disabled";
441
442 pcie_port: pcie-phy@11c00000 {
443 reg = <0 0x11c00000 0 0x20000>;
444 clocks = <&clk40m>;
445 clock-names = "ref";
446 #phy-cells = <1>;
447 auto_load_valid;
448 auto_load_valid_ln1;
449 nvmem-cells = <&pcie_intr_ln0>,
450 <&pcie_rx_imp_ln0>,
451 <&pcie_tx_imp_ln0>,
452 <&pcie_auto_load_valid_ln0>,
453 <&pcie_intr_ln1>,
454 <&pcie_rx_imp_ln1>,
455 <&pcie_tx_imp_ln1>,
456 <&pcie_auto_load_valid_ln1>;
457 nvmem-cell-names = "intr",
458 "rx_imp",
459 "tx_imp",
460 "auto_load_valid",
461 "intr_ln1",
462 "rx_imp_ln1",
463 "tx_imp_ln1",
464 "auto_load_valid_ln1";
465 };
466 };
467
468 efuse: efuse@11d00000 {
469 compatible = "mediatek,mt7986-efuse",
470 "mediatek,efuse";
471 reg = <0 0x11d00000 0 0x1000>;
472 #address-cells = <1>;
473 #size-cells = <1>;
474
475 thermal_calibration: calib@274 {
476 reg = <0x274 0xc>;
477 };
478
479 comb_auto_load_valid: usb3-alv-imp@8da {
480 reg = <0x8da 1>;
481 bits = <0 1>;
482 };
483
484 comb_rx_imp_p0: usb3-rx-imp@8d8 {
485 reg = <0x8d8 1>;
486 bits = <0 5>;
487 };
488
489 comb_tx_imp_p0: usb3-tx-imp@8d8 {
490 reg = <0x8d8 2>;
491 bits = <5 5>;
492 };
493
494 comb_intr_p0: usb3-intr@8d9 {
495 reg = <0x8d9 1>;
496 bits = <2 6>;
497 };
498
499 u2_auto_load_valid_p0: usb2-alv-p0@8e0 {
500 reg = <0x8e0 1>;
501 bits = <0 1>;
502 };
503
504 u2_intr_p0: usb2-intr-p0@8e0 {
505 reg = <0x8e0 1>;
506 bits = <1 5>;
507 };
508
509 u2_auto_load_valid_p1: usb2-alv-p1@8e0 {
510 reg = <0x8e0 2>;
511 bits = <6 1>;
512 };
513
514 u2_intr_p1: usb2-intr-p1@8e0 {
515 reg = <0x8e0 2>;
516 bits = <7 5>;
517 };
518
519 pcie_rx_imp_ln0: pcie-rx-imp@8d0 {
520 reg = <0x8d0 1>;
521 bits = <0 5>;
522 };
523
524 pcie_tx_imp_ln0: pcie-tx-imp@8d0 {
525 reg = <0x8d0 2>;
526 bits = <5 5>;
527 };
528
529 pcie_intr_ln0: pcie-intr@8d1 {
530 reg = <0x8d1 1>;
531 bits = <2 6>;
532 };
533
534 pcie_auto_load_valid_ln0: pcie-ln0-alv@8d4 {
535 reg = <0x8d4 1>;
536 bits = <0 1>;
537 };
538
539 pcie_rx_imp_ln1: pcie-rx-imp@8d2 {
540 reg = <0x8d2 1>;
541 bits = <0 5>;
542 };
543
544 pcie_tx_imp_ln1: pcie-tx-imp@8d2 {
545 reg = <0x8d2 2>;
546 bits = <5 5>;
547 };
548
549 pcie_intr_ln1: pcie-intr@8d3 {
550 reg = <0x8d3 1>;
551 bits = <2 6>;
552 };
553
554 pcie_auto_load_valid_ln1: pcie-ln1-alv@8d4 {
555 reg = <0x8d4 1>;
556 bits = <1 1>;
557 };
558 };
559
560 usb_phy: t-phy@11e10000 {
561 compatible = "mediatek,mt7986-tphy",
562 "mediatek,generic-tphy-v2";
563 #address-cells = <2>;
564 #size-cells = <2>;
565 ranges;
566 status = "disabled";
567
568 u2port0: usb-phy@11e10000 {
569 reg = <0 0x11e10000 0 0x700>;
570 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
571 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
572 clock-names = "ref", "da_ref";
573 #phy-cells = <1>;
574 auto_load_valid;
575 nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
576 nvmem-cell-names = "intr", "auto_load_valid";
577 };
578
579 u3port0: usb-phy@11e10700 {
580 reg = <0 0x11e10700 0 0x900>;
581 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
582 clock-names = "ref";
583 #phy-cells = <1>;
584 auto_load_valid;
585 nvmem-cells = <&comb_intr_p0>,
586 <&comb_rx_imp_p0>,
587 <&comb_tx_imp_p0>,
588 <&comb_auto_load_valid>;
589 nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
590 };
591
592 u2port1: usb-phy@11e11000 {
593 reg = <0 0x11e11000 0 0x700>;
594 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
595 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
596 clock-names = "ref", "da_ref";
597 #phy-cells = <1>;
598 auto_load_valid;
599 nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>;
600 nvmem-cell-names = "intr", "auto_load_valid";
601 };
602 };
603
604 ethsys: syscon@15000000 {
605 #address-cells = <1>;
606 #size-cells = <1>;
607 compatible = "mediatek,mt7986-ethsys_ck",
608 "syscon";
609 reg = <0 0x15000000 0 0x1000>;
610 #clock-cells = <1>;
611 #reset-cells = <1>;
612 };
613
614 wed_pcie: wed-pcie@10003000 {
615 compatible = "mediatek,mt7986-wed-pcie",
616 "syscon";
617 reg = <0 0x10003000 0 0x10>;
618 };
619
620
621 wed0: wed@15010000 {
622 compatible = "mediatek,mt7986-wed",
623 "syscon";
624 reg = <0 0x15010000 0 0x1000>;
625 interrupt-parent = <&gic>;
626 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
627 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
628 <&wo_data>, <&wo_boot>;
629 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
630 "wo-data", "wo-boot";
631 mediatek,wo-ccif = <&wo_ccif0>;
632 };
633
634 wed1: wed@15011000 {
635 compatible = "mediatek,mt7986-wed",
636 "syscon";
637 reg = <0 0x15011000 0 0x1000>;
638 interrupt-parent = <&gic>;
639 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
640 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
641 <&wo_data>, <&wo_boot>;
642 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
643 "wo-data", "wo-boot";
644 mediatek,wo-ccif = <&wo_ccif1>;
645 };
646
647 wo_ccif0: syscon@151a5000 {
648 compatible = "mediatek,mt7986-wo-ccif", "syscon";
649 reg = <0 0x151a5000 0 0x1000>;
650 interrupt-parent = <&gic>;
651 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
652 };
653
654 wo_ccif1: syscon@151ad000 {
655 compatible = "mediatek,mt7986-wo-ccif", "syscon";
656 reg = <0 0x151ad000 0 0x1000>;
657 interrupt-parent = <&gic>;
658 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
659 };
660
661 eth: ethernet@15100000 {
662 compatible = "mediatek,mt7986-eth";
663 reg = <0 0x15100000 0 0x80000>;
664 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&ethsys CLK_ETH_FE_EN>,
669 <&ethsys CLK_ETH_GP2_EN>,
670 <&ethsys CLK_ETH_GP1_EN>,
671 <&ethsys CLK_ETH_WOCPU1_EN>,
672 <&ethsys CLK_ETH_WOCPU0_EN>,
673 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
674 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
675 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
676 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
677 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
678 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
679 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
680 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
681 <&topckgen CLK_TOP_NETSYS_SEL>,
682 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
683 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
684 "sgmii_tx250m", "sgmii_rx250m",
685 "sgmii_cdr_ref", "sgmii_cdr_fb",
686 "sgmii2_tx250m", "sgmii2_rx250m",
687 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
688 "netsys0", "netsys1";
689 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
690 <&topckgen CLK_TOP_SGM_325M_SEL>;
691 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
692 <&apmixedsys CLK_APMIXED_SGMPLL>;
693 mediatek,ethsys = <&ethsys>;
694 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
695 mediatek,wed-pcie = <&wed_pcie>;
696 mediatek,wed = <&wed0>, <&wed1>;
697 #reset-cells = <1>;
698 #address-cells = <1>;
699 #size-cells = <0>;
700 status = "disabled";
701 };
702
703 consys: consys@10000000 {
704 compatible = "mediatek,mt7986-consys";
705 reg = <0 0x10000000 0 0x8600000>;
706 memory-region = <&wmcpu_emi>;
707 };
708
709 wmac: wmac@18000000 {
710 compatible = "mediatek,mt7986-wmac", "mediatek,wbsys";
711 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
712 reset-names = "consys";
713 reg = <0 0x18000000 0 0x1000000>,
714 <0 0x10003000 0 0x1000>,
715 <0 0x11d10000 0 0x1000>;
716 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
721 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
722 clock-names = "mcu", "ap2conn";
723 memory-region = <&wmcpu_emi>;
724 status = "disabled";
725 };
726 };
727
728 fan: pwm-fan {
729 compatible = "pwm-fan";
730 /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */
731 cooling-levels = <0 86 172 255>;
732 #cooling-cells = <2>;
733 status = "disabled";
734 };
735
736 thermal-zones {
737 cpu_thermal: cpu-thermal {
738 polling-delay-passive = <1000>;
739 polling-delay = <1000>;
740 thermal-sensors = <&thermal 0>;
741 trips {
742 cpu_trip_crit: crit {
743 temperature = <125000>;
744 hysteresis = <2000>;
745 type = "critical";
746 };
747
748 cpu_trip_hot: hot {
749 temperature = <120000>;
750 hysteresis = <2000>;
751 type = "hot";
752 };
753
754 cpu_trip_active_high: active-high {
755 temperature = <115000>;
756 hysteresis = <2000>;
757 type = "active";
758 };
759
760 cpu_trip_active_med: active-med {
761 temperature = <85000>;
762 hysteresis = <2000>;
763 type = "active";
764 };
765
766 cpu_trip_active_low: active-low {
767 temperature = <60000>;
768 hysteresis = <2000>;
769 type = "passive";
770 };
771 };
772
773 cooling-maps {
774 cpu-active-high {
775 /* active: set fan to cooling level 3 */
776 cooling-device = <&fan 3 3>;
777 trip = <&cpu_trip_active_high>;
778 };
779
780 cpu-active-med {
781 /* active: set fan to cooling level 2 */
782 cooling-device = <&fan 2 2>;
783 trip = <&cpu_trip_active_med>;
784 };
785
786 cpu-active-low {
787 /* passive: set fan to cooling level 1 */
788 cooling-device = <&fan 1 1>;
789 trip = <&cpu_trip_active_low>;
790 };
791 };
792 };
793 };
794 };
Staging tree of Sander Vanheule