target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2022 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "mt7988a-rfb-spim-nand.dtsi"
   9 #include <dt-bindings/pinctrl/mt65xx.h>
  10 #include <dt-bindings/leds/common.h>
  11
  12 / {
  13         model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
  14         compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
  15                      "mediatek,mt7988a-rfb-snand",
  16                      "mediatek,mt7988";
  17
  18         chosen {
  19                 bootargs = "console=ttyS0,115200n1 loglevel=8  \
  20                             earlycon=uart8250,mmio32,0x11000000 \
  21                             pci=pcie_bus_perf";
  22         };
  23
  24         memory {
  25                 reg = <0 0x40000000 0 0x40000000>;
  26         };
  27 };
  28
  29 &eth {
  30         pinctrl-0 = <&mdio0_pins>;
  31         pinctrl-names = "default";
  32         status = "okay";
  33 };
  34
  35 &gmac0 {
  36         status = "okay";
  37 };
  38
  39 &gmac1 {
  40         status = "okay";
  41         phy-mode = "internal";
  42         phy-connection-type = "internal";
  43         phy = <&int_2p5g_phy>;
  44 };
  45
  46 &gmac2 {
  47         status = "okay";
  48         phy-mode = "usxgmii";
  49         phy-connection-type = "usxgmii";
  50         phy = <&phy8>;
  51 };
  52
  53 &mdio_bus {
  54         /* external Aquantia AQR113C */
  55         phy0: ethernet-phy@0 {
  56                 reg = <0>;
  57                 compatible = "ethernet-phy-ieee802.3-c45";
  58                 reset-gpios = <&pio 72 1>;
  59                 reset-assert-us = <100000>;
  60                 reset-deassert-us = <221000>;
  61         };
  62
  63         /* external Aquantia AQR113C */
  64         phy8: ethernet-phy@8 {
  65                 reg = <8>;
  66                 compatible = "ethernet-phy-ieee802.3-c45";
  67                 reset-gpios = <&pio 71 1>;
  68                 reset-assert-us = <100000>;
  69                 reset-deassert-us = <221000>;
  70         };
  71
  72         /* external Maxlinear GPY211C */
  73         phy5: ethernet-phy@5 {
  74                 reg = <5>;
  75                 compatible = "ethernet-phy-ieee802.3-c45";
  76                 phy-mode = "2500base-x";
  77         };
  78
  79         /* external Maxlinear GPY211C */
  80         phy13: ethernet-phy@13 {
  81                 reg = <13>;
  82                 compatible = "ethernet-phy-ieee802.3-c45";
  83                 phy-mode = "2500base-x";
  84         };
  85 };
  86
  87 &int_2p5g_phy {
  88         pinctrl-names = "i2p5gbe-led";
  89         pinctrl-0 = <&i2p5gbe_led0_pins>;
  90 };
  91
  92 &switch {
  93         status = "okay";
  94 };
  95
  96 &gsw_phy0 {
  97         pinctrl-names = "gbe-led";
  98         pinctrl-0 = <&gbe0_led0_pins>;
  99 };
 100
 101 &gsw_phy0_led0 {
 102         status = "okay";
 103         color = <LED_COLOR_ID_GREEN>;
 104 };
 105
 106 &gsw_phy1 {
 107         pinctrl-names = "gbe-led";
 108         pinctrl-0 = <&gbe1_led0_pins>;
 109 };
 110
 111 &gsw_phy1_led0 {
 112         status = "okay";
 113         color = <LED_COLOR_ID_GREEN>;
 114 };
 115
 116 &gsw_phy2 {
 117         pinctrl-names = "gbe-led";
 118         pinctrl-0 = <&gbe2_led0_pins>;
 119 };
 120
 121 &gsw_phy2_led0 {
 122         status = "okay";
 123         color = <LED_COLOR_ID_GREEN>;
 124 };
 125
 126 &gsw_phy3 {
 127         pinctrl-names = "gbe-led";
 128         pinctrl-0 = <&gbe3_led0_pins>;
 129 };
 130
 131 &gsw_phy3_led0 {
 132         status = "okay";
 133         color = <LED_COLOR_ID_GREEN>;
 134 };