target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2022 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "mt7988a-rfb-spim-nand.dtsi"
   9 #include <dt-bindings/pinctrl/mt65xx.h>
  10
  11 / {
  12         model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
  13         compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
  14                      "mediatek,mt7988a-rfb-snand",
  15                      "mediatek,mt7988";
  16
  17         chosen {
  18                 bootargs = "console=ttyS0,115200n1 loglevel=8  \
  19                             earlycon=uart8250,mmio32,0x11000000 \
  20                             pci=pcie_bus_perf";
  21         };
  22
  23         memory {
  24                 reg = <0 0x40000000 0 0x40000000>;
  25         };
  26 };
  27
  28 &eth {
  29         pinctrl-0 = <&mdio0_pins>;
  30         pinctrl-names = "default";
  31         status = "okay";
  32
  33         gmac0: mac@0 {
  34                 compatible = "mediatek,eth-mac";
  35                 reg = <0>;
  36                 phy-mode = "internal";
  37
  38                 fixed-link {
  39                         speed = <10000>;
  40                         full-duplex;
  41                         pause;
  42                 };
  43         };
  44
  45         gmac1: mac@1 {
  46                 compatible = "mediatek,eth-mac";
  47                 reg = <1>;
  48                 phy-mode = "internal";
  49                 phy-connection-type = "internal";
  50                 phy = <&phy15>;
  51         };
  52
  53         gmac2: mac@2 {
  54                 compatible = "mediatek,eth-mac";
  55                 reg = <2>;
  56                 phy-mode = "10gbase-kr";
  57                 phy-connection-type = "10gbase-kr";
  58                 phy = <&phy8>;
  59         };
  60
  61         mdio0: mdio-bus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 /* external Aquantia AQR113C */
  66                 phy0: ethernet-phy@0 {
  67                         reg = <0>;
  68                         compatible = "ethernet-phy-ieee802.3-c45";
  69                         reset-gpios = <&pio 72 1>;
  70                         reset-assert-us = <100000>;
  71                         reset-deassert-us = <221000>;
  72                 };
  73
  74                 /* external Aquantia AQR113C */
  75                 phy8: ethernet-phy@8 {
  76                         reg = <8>;
  77                         compatible = "ethernet-phy-ieee802.3-c45";
  78                         reset-gpios = <&pio 71 1>;
  79                         reset-assert-us = <100000>;
  80                         reset-deassert-us = <221000>;
  81                 };
  82
  83                 /* external Maxlinear GPY211C */
  84                 phy5: ethernet-phy@5 {
  85                         reg = <5>;
  86                         compatible = "ethernet-phy-ieee802.3-c45";
  87                         phy-mode = "2500base-x";
  88                 };
  89
  90                 /* external Maxlinear GPY211C */
  91                 phy13: ethernet-phy@13 {
  92                         reg = <13>;
  93                         compatible = "ethernet-phy-ieee802.3-c45";
  94                         phy-mode = "2500base-x";
  95                 };
  96
  97                 /* internal 2.5G PHY */
  98                 phy15: ethernet-phy@15 {
  99                         reg = <15>;
 100                         pinctrl-names = "i2p5gbe-led";
 101                         pinctrl-0 = <&i2p5gbe_led0_pins>;
 102                         compatible = "ethernet-phy-ieee802.3-c45";
 103                         phy-mode = "internal";
 104                 };
 105         };
 106 };
 107
 108 &switch {
 109         status = "okay";
 110
 111         ports {
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114
 115                 port@0 {
 116                         reg = <0>;
 117                         label = "lan0";
 118                         phy-mode = "internal";
 119                         phy-handle = <&gsw_phy0>;
 120                 };
 121
 122                 port@1 {
 123                         reg = <1>;
 124                         label = "lan1";
 125                         phy-mode = "internal";
 126                         phy-handle = <&gsw_phy1>;
 127                 };
 128
 129                 port@2 {
 130                         reg = <2>;
 131                         label = "lan2";
 132                         phy-mode = "internal";
 133                         phy-handle = <&gsw_phy2>;
 134                 };
 135
 136                 port@3 {
 137                         reg = <3>;
 138                         label = "lan3";
 139                         phy-mode = "internal";
 140                         phy-handle = <&gsw_phy3>;
 141                 };
 142
 143                 port@6 {
 144                         reg = <6>;
 145                         ethernet = <&gmac0>;
 146                         phy-mode = "internal";
 147
 148                         fixed-link {
 149                                 speed = <10000>;
 150                                 full-duplex;
 151                                 pause;
 152                         };
 153                 };
 154         };
 155
 156         mdio {
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 mediatek,pio = <&pio>;
 160
 161                 gsw_phy0: ethernet-phy@0 {
 162                         compatible = "ethernet-phy-id03a2.9481";
 163                         reg = <0>;
 164                         phy-mode = "internal";
 165                         pinctrl-names = "gbe-led";
 166                         pinctrl-0 = <&gbe0_led0_pins>;
 167                         nvmem-cells = <&phy_calibration_p0>;
 168                         nvmem-cell-names = "phy-cal-data";
 169                 };
 170
 171                 gsw_phy1: ethernet-phy@1 {
 172                         compatible = "ethernet-phy-id03a2.9481";
 173                         reg = <1>;
 174                         phy-mode = "internal";
 175                         pinctrl-names = "gbe-led";
 176                         pinctrl-0 = <&gbe1_led0_pins>;
 177                         nvmem-cells = <&phy_calibration_p1>;
 178                         nvmem-cell-names = "phy-cal-data";
 179                 };
 180
 181                 gsw_phy2: ethernet-phy@2 {
 182                         compatible = "ethernet-phy-id03a2.9481";
 183                         reg = <2>;
 184                         phy-mode = "internal";
 185                         pinctrl-names = "gbe-led";
 186                         pinctrl-0 = <&gbe2_led0_pins>;
 187                         nvmem-cells = <&phy_calibration_p2>;
 188                         nvmem-cell-names = "phy-cal-data";
 189                 };
 190
 191                 gsw_phy3: ethernet-phy@3 {
 192                         compatible = "ethernet-phy-id03a2.9481";
 193                         reg = <3>;
 194                         phy-mode = "internal";
 195                         pinctrl-names = "gbe-led";
 196                         pinctrl-0 = <&gbe3_led0_pins>;
 197                         nvmem-cells = <&phy_calibration_p3>;
 198                         nvmem-cell-names = "phy-cal-data";
 199                 };
 200         };
 201 };