1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/ti-syscon.h>
14 #include <dt-bindings/thermal/thermal.h>
17 compatible = "mediatek,mt7988";
18 interrupt-parent = <&gic>;
23 compatible = "mediatek,mt7988-cci",
24 "mediatek,mt8183-cci";
25 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
26 <&topckgen CLK_TOP_XTAL>;
27 clock-names = "cci", "intermediate";
28 operating-points-v2 = <&cci_opp>;
36 compatible = "arm,cortex-a73";
39 enable-method = "psci";
40 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
41 <&topckgen CLK_TOP_XTAL>;
42 clock-names = "cpu", "intermediate";
43 operating-points-v2 = <&cluster0_opp>;
44 mediatek,cci = <&cci>;
48 compatible = "arm,cortex-a73";
51 enable-method = "psci";
52 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
53 <&topckgen CLK_TOP_XTAL>;
54 clock-names = "cpu", "intermediate";
55 operating-points-v2 = <&cluster0_opp>;
56 mediatek,cci = <&cci>;
60 compatible = "arm,cortex-a73";
63 enable-method = "psci";
64 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
65 <&topckgen CLK_TOP_XTAL>;
66 clock-names = "cpu", "intermediate";
67 operating-points-v2 = <&cluster0_opp>;
68 mediatek,cci = <&cci>;
72 compatible = "arm,cortex-a73";
75 enable-method = "psci";
76 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
77 <&topckgen CLK_TOP_XTAL>;
78 clock-names = "cpu", "intermediate";
79 operating-points-v2 = <&cluster0_opp>;
80 mediatek,cci = <&cci>;
83 cluster0_opp: opp_table0 {
84 compatible = "operating-points-v2";
88 opp-hz = /bits/ 64 <800000000>;
89 opp-microvolt = <850000>;
93 opp-hz = /bits/ 64 <1100000000>;
94 opp-microvolt = <850000>;
98 opp-hz = /bits/ 64 <1500000000>;
99 opp-microvolt = <850000>;
103 opp-hz = /bits/ 64 <1800000000>;
104 opp-microvolt = <900000>;
109 cci_opp: opp_table_cci {
110 compatible = "operating-points-v2";
114 opp-hz = /bits/ 64 <480000000>;
115 opp-microvolt = <850000>;
119 opp-hz = /bits/ 64 <660000000>;
120 opp-microvolt = <850000>;
124 opp-hz = /bits/ 64 <900000000>;
125 opp-microvolt = <850000>;
129 opp-hz = /bits/ 64 <1080000000>;
130 opp-microvolt = <900000>;
134 clk40m: oscillator@0 {
135 compatible = "fixed-clock";
136 clock-frequency = <40000000>;
138 clock-output-names = "clkxtal";
142 compatible = "arm,cortex-a73-pmu";
143 interrupt-parent = <&gic>;
144 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
148 compatible = "arm,psci-0.2";
152 reg_1p8v: regulator-1p8v {
153 compatible = "regulator-fixed";
154 regulator-name = "fixed-1.8V";
155 regulator-min-microvolt = <1800000>;
156 regulator-max-microvolt = <1800000>;
161 reg_3p3v: regulator-3p3v {
162 compatible = "regulator-fixed";
163 regulator-name = "fixed-3.3V";
164 regulator-min-microvolt = <3300000>;
165 regulator-max-microvolt = <3300000>;
172 #address-cells = <2>;
175 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
176 secmon_reserved: secmon@43000000 {
177 reg = <0 0x43000000 0 0x50000>;
183 compatible = "simple-bus";
185 #address-cells = <2>;
188 gic: interrupt-controller@c000000 {
189 compatible = "arm,gic-v3";
190 reg = <0 0x0c000000 0 0x40000>, /* GICD */
191 <0 0x0c080000 0 0x200000>, /* GICR */
192 <0 0x0c400000 0 0x2000>, /* GICC */
193 <0 0x0c410000 0 0x1000>, /* GICH */
194 <0 0x0c420000 0 0x2000>; /* GICV */
195 interrupt-parent = <&gic>;
196 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
197 interrupt-controller;
198 #interrupt-cells = <3>;
201 phyfw: phy-firmware@f000000 {
202 compatible = "mediatek,2p5gphy-fw";
203 reg = <0 0x0f000000 0 0x8000>,
204 <0 0x0f100000 0 0x20000>,
205 <0 0x0f0f0000 0 0x200>;
208 infracfg: infracfg@10001000 {
209 compatible = "mediatek,mt7988-infracfg", "syscon";
210 reg = <0 0x10001000 0 0x1000>;
214 topckgen: topckgen@1001b000 {
215 compatible = "mediatek,mt7988-topckgen", "syscon";
216 reg = <0 0x1001b000 0 0x1000>;
220 watchdog: watchdog@1001c000 {
221 compatible = "mediatek,mt7988-wdt",
222 "mediatek,mt6589-wdt",
224 reg = <0 0x1001c000 0 0x1000>;
225 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
229 apmixedsys: apmixedsys@1001e000 {
230 compatible = "mediatek,mt7988-apmixedsys";
231 reg = <0 0x1001e000 0 0x1000>;
235 pio: pinctrl@1001f000 {
236 compatible = "mediatek,mt7988-pinctrl", "syscon";
237 reg = <0 0x1001f000 0 0x1000>,
238 <0 0x11c10000 0 0x1000>,
239 <0 0x11d00000 0 0x1000>,
240 <0 0x11d20000 0 0x1000>,
241 <0 0x11e00000 0 0x1000>,
242 <0 0x11f00000 0 0x1000>,
243 <0 0x1000b000 0 0x1000>;
244 reg-names = "gpio_base", "iocfg_tr_base",
245 "iocfg_br_base", "iocfg_rb_base",
246 "iocfg_lb_base", "iocfg_tl_base", "eint";
249 gpio-ranges = <&pio 0 0 84>;
250 interrupt-controller;
251 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
252 interrupt-parent = <&gic>;
253 #interrupt-cells = <2>;
255 mdio0_pins: mdio0-pins {
258 groups = "mdc_mdio0";
262 groups = "mdc_mdio0";
263 drive-strength = <MTK_DRIVE_8mA>;
267 i2c0_pins: i2c0-pins-g0 {
274 i2c1_pins: i2c1-pins-g0 {
281 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
288 i2c2_pins: i2c2-pins {
295 i2c2_0_pins: i2c2-pins-g0 {
302 i2c2_1_pins: i2c2-pins-g1 {
309 gbe0_led0_pins: gbe0-led0-pins {
312 groups = "gbe0_led0";
316 gbe1_led0_pins: gbe1-led0-pins {
319 groups = "gbe1_led0";
323 gbe2_led0_pins: gbe2-led0-pins {
326 groups = "gbe2_led0";
330 gbe3_led0_pins: gbe3-led0-pins {
333 groups = "gbe3_led0";
337 gbe0_led1_pins: gbe0-led1-pins {
340 groups = "gbe0_led1";
344 gbe1_led1_pins: gbe1-led1-pins {
347 groups = "gbe1_led1";
351 gbe2_led1_pins: gbe2-led1-pins {
354 groups = "gbe2_led1";
358 gbe3_led1_pins: gbe3-led1-pins {
361 groups = "gbe3_led1";
365 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
368 groups = "2p5gbe_led0";
372 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
375 groups = "2p5gbe_led1";
379 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
386 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
393 mmc0_pins_sdcard: mmc0-pins-sdcard {
400 uart0_pins: uart0-pins {
407 snfi_pins: snfi-pins {
414 spi0_pins: spi0-pins {
421 spi0_flash_pins: spi0-flash-pins {
424 groups = "spi0", "spi0_wp_hold";
428 spi1_pins: spi1-pins {
435 spi2_pins: spi2-pins {
442 spi2_flash_pins: spi2-flash-pins {
445 groups = "spi2", "spi2_wp_hold";
449 pcie0_pins: pcie0-pins {
452 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
457 pcie1_pins: pcie1-pins {
460 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
465 pcie2_pins: pcie2-pins {
468 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
473 pcie3_pins: pcie3-pins {
476 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
483 compatible = "mediatek,mt7988-pwm";
484 reg = <0 0x10048000 0 0x1000>;
486 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
487 <&infracfg CLK_INFRA_66M_PWM_HCK>,
488 <&infracfg CLK_INFRA_66M_PWM_CK1>,
489 <&infracfg CLK_INFRA_66M_PWM_CK2>,
490 <&infracfg CLK_INFRA_66M_PWM_CK3>,
491 <&infracfg CLK_INFRA_66M_PWM_CK4>,
492 <&infracfg CLK_INFRA_66M_PWM_CK5>,
493 <&infracfg CLK_INFRA_66M_PWM_CK6>,
494 <&infracfg CLK_INFRA_66M_PWM_CK7>,
495 <&infracfg CLK_INFRA_66M_PWM_CK8>;
496 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
497 "pwm4","pwm5","pwm6","pwm7","pwm8";
501 sgmiisys0: syscon@10060000 {
502 compatible = "mediatek,mt7988-sgmiisys",
503 "mediatek,mt7988-sgmiisys_0",
505 reg = <0 0x10060000 0 0x1000>;
509 sgmiisys1: syscon@10070000 {
510 compatible = "mediatek,mt7988-sgmiisys",
511 "mediatek,mt7988-sgmiisys_1",
513 reg = <0 0x10070000 0 0x1000>;
517 usxgmiisys0: usxgmiisys@10080000 {
518 compatible = "mediatek,mt7988-usxgmiisys",
519 "mediatek,mt7988-usxgmiisys_0",
521 reg = <0 0x10080000 0 0x1000>;
525 usxgmiisys1: usxgmiisys@10081000 {
526 compatible = "mediatek,mt7988-usxgmiisys",
527 "mediatek,mt7988-usxgmiisys_1",
529 reg = <0 0x10081000 0 0x1000>;
533 mcusys: mcusys@100e0000 {
534 compatible = "mediatek,mt7988-mcusys", "syscon";
535 reg = <0 0x100e0000 0 0x1000>;
539 uart0: serial@11000000 {
540 compatible = "mediatek,mt7986-uart",
541 "mediatek,mt6577-uart";
542 reg = <0 0x11000000 0 0x100>;
543 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
545 * 8250-mtk driver don't control "baud" clock since commit
546 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
547 * still need to be passed to the driver to prevent probe fail
549 clocks = <&topckgen CLK_TOP_UART_SEL>,
550 <&infracfg CLK_INFRA_52M_UART0_CK>;
551 clock-names = "baud", "bus";
552 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
553 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
554 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
555 <&topckgen CLK_TOP_UART_SEL>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart0_pins>;
561 snand: spi@11001000 {
562 compatible = "mediatek,mt7986-snand";
563 reg = <0 0x11001000 0 0x1000>;
564 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&infracfg CLK_INFRA_SPINFI>,
566 <&infracfg CLK_INFRA_NFI>;
567 clock-names = "pad_clk", "nfi_clk";
568 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
569 <&topckgen CLK_TOP_NFI1X_SEL>;
570 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
571 <&topckgen CLK_TOP_MPLL_D8>;
572 nand-ecc-engine = <&bch>;
574 #address-cells = <1>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&snfi_pins>;
582 compatible = "mediatek,mt7686-ecc";
583 reg = <0 0x11002000 0 0x1000>;
584 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
586 clock-names = "nfiecc_clk";
591 compatible = "mediatek,mt7988-i2c",
592 "mediatek,mt7981-i2c";
593 reg = <0 0x11003000 0 0x1000>,
594 <0 0x10217080 0 0x80>;
595 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
598 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
599 clock-names = "main", "dma";
600 #address-cells = <1>;
606 compatible = "mediatek,mt7988-i2c",
607 "mediatek,mt7981-i2c";
608 reg = <0 0x11004000 0 0x1000>,
609 <0 0x10217100 0 0x80>;
610 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
613 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
614 clock-names = "main", "dma";
615 #address-cells = <1>;
621 compatible = "mediatek,mt7988-i2c",
622 "mediatek,mt7981-i2c";
623 reg = <0 0x11005000 0 0x1000>,
624 <0 0x10217180 0 0x80>;
625 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
628 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
629 clock-names = "main", "dma";
630 #address-cells = <1>;
636 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
637 reg = <0 0x11007000 0 0x100>;
638 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&topckgen CLK_TOP_MPLL_D2>,
640 <&topckgen CLK_TOP_SPI_SEL>,
641 <&infracfg CLK_INFRA_104M_SPI0>,
642 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
643 clock-names = "parent-clk", "sel-clk", "spi-clk",
645 #address-cells = <1>;
651 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
652 reg = <0 0x11008000 0 0x100>;
653 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&topckgen CLK_TOP_MPLL_D2>,
655 <&topckgen CLK_TOP_SPI_SEL>,
656 <&infracfg CLK_INFRA_104M_SPI1>,
657 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
658 clock-names = "parent-clk", "sel-clk", "spi-clk",
660 #address-cells = <1>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&spi1_pins>;
668 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
669 reg = <0 0x11009000 0 0x100>;
670 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&topckgen CLK_TOP_MPLL_D2>,
672 <&topckgen CLK_TOP_SPI_SEL>,
673 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
674 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
675 clock-names = "parent-clk", "sel-clk", "spi-clk",
677 #address-cells = <1>;
683 compatible = "pwm-fan";
684 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
685 cooling-levels = <0 128 255>;
686 #cooling-cells = <2>;
687 #thermal-sensor-cells = <1>;
691 lvts: lvts@1100a000 {
692 compatible = "mediatek,mt7988-lvts";
693 reg = <0 0x1100a000 0 0x1000>;
694 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
695 clock-names = "lvts_clk";
696 nvmem-cells = <&lvts_calibration>;
697 nvmem-cell-names = "e_data1";
698 #thermal-sensor-cells = <1>;
701 ssusb0: usb@11190000 {
702 compatible = "mediatek,mt7988-xhci",
704 reg = <0 0x11190000 0 0x2e00>,
705 <0 0x11193e00 0 0x0100>;
706 reg-names = "mac", "ippc";
707 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
708 phys = <&xphyu2port0 PHY_TYPE_USB2>,
709 <&xphyu3port0 PHY_TYPE_USB3>;
710 clocks = <&infracfg CLK_INFRA_USB_SYS>,
711 <&infracfg CLK_INFRA_USB_XHCI>,
712 <&infracfg CLK_INFRA_USB_REF>,
713 <&infracfg CLK_INFRA_66M_USB_HCK>,
714 <&infracfg CLK_INFRA_133M_USB_HCK>;
715 clock-names = "sys_ck",
720 #address-cells = <2>;
722 mediatek,p0_speed_fixup;
726 ssusb1: usb@11200000 {
727 compatible = "mediatek,mt7988-xhci",
729 reg = <0 0x11200000 0 0x2e00>,
730 <0 0x11203e00 0 0x0100>;
731 reg-names = "mac", "ippc";
732 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
733 phys = <&tphyu2port0 PHY_TYPE_USB2>,
734 <&tphyu3port0 PHY_TYPE_USB3>;
735 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
736 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
737 <&infracfg CLK_INFRA_USB_CK_P1>,
738 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
739 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
740 clock-names = "sys_ck",
745 #address-cells = <2>;
750 afe: audio-controller@11210000 {
751 compatible = "mediatek,mt79xx-audio";
752 reg = <0 0x11210000 0 0x9000>;
753 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
755 <&infracfg CLK_INFRA_AUD_26M>,
756 <&infracfg CLK_INFRA_AUD_L>,
757 <&infracfg CLK_INFRA_AUD_AUD>,
758 <&infracfg CLK_INFRA_AUD_EG2>,
759 <&topckgen CLK_TOP_AUD_SEL>,
760 <&topckgen CLK_TOP_AUD_I2S_M>;
761 clock-names = "aud_bus_ck",
768 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
769 <&topckgen CLK_TOP_A1SYS_SEL>,
770 <&topckgen CLK_TOP_AUD_L_SEL>,
771 <&topckgen CLK_TOP_A_TUNER_SEL>;
772 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
773 <&topckgen CLK_TOP_APLL2_D4>,
774 <&apmixedsys CLK_APMIXED_APLL2>,
775 <&topckgen CLK_TOP_APLL2_D4>;
780 compatible = "mediatek,mt7986-mmc",
781 "mediatek,mt7981-mmc";
782 reg = <0 0x11230000 0 0x1000>,
783 <0 0x11D60000 0 0x1000>;
784 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&infracfg CLK_INFRA_MSDC400>,
786 <&infracfg CLK_INFRA_MSDC2_HCK>,
787 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
788 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
789 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
790 <&topckgen CLK_TOP_EMMC_400M_SEL>;
791 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
792 <&apmixedsys CLK_APMIXED_MSDCPLL>;
793 clock-names = "source",
797 #address-cells = <1>;
802 pcie2: pcie@11280000 {
803 compatible = "mediatek,mt7988-pcie",
804 "mediatek,mt7986-pcie",
805 "mediatek,mt8192-pcie";
806 reg = <0 0x11280000 0 0x2000>;
807 reg-names = "pcie-mac";
808 ranges = <0x81000000 0x00 0x20000000 0x00
809 0x20000000 0x00 0x00200000>,
810 <0x82000000 0x00 0x20200000 0x00
811 0x20200000 0x00 0x07e00000>;
813 linux,pci-domain = <3>;
814 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
815 bus-range = <0x00 0xff>;
816 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
817 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
818 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
819 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
820 clock-names = "pl_250m", "tl_26m", "peri_26m",
822 pinctrl-names = "default";
823 pinctrl-0 = <&pcie2_pins>;
824 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
825 phy-names = "pcie-phy";
826 #interrupt-cells = <1>;
827 interrupt-map-mask = <0 0 0 0x7>;
828 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
829 <0 0 0 2 &pcie_intc2 1>,
830 <0 0 0 3 &pcie_intc2 2>,
831 <0 0 0 4 &pcie_intc2 3>;
832 #address-cells = <3>;
836 pcie_intc2: interrupt-controller {
837 #address-cells = <0>;
838 #interrupt-cells = <1>;
839 interrupt-controller;
843 pcie3: pcie@11290000 {
844 compatible = "mediatek,mt7988-pcie",
845 "mediatek,mt7986-pcie",
846 "mediatek,mt8192-pcie";
847 reg = <0 0x11290000 0 0x2000>;
848 reg-names = "pcie-mac";
849 ranges = <0x81000000 0x00 0x28000000 0x00
850 0x28000000 0x00 0x00200000>,
851 <0x82000000 0x00 0x28200000 0x00
852 0x28200000 0x00 0x07e00000>;
854 linux,pci-domain = <2>;
855 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
856 bus-range = <0x00 0xff>;
857 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
858 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
859 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
860 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
861 clock-names = "pl_250m", "tl_26m", "peri_26m",
863 pinctrl-names = "default";
864 pinctrl-0 = <&pcie3_pins>;
865 #interrupt-cells = <1>;
866 interrupt-map-mask = <0 0 0 0x7>;
867 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
868 <0 0 0 2 &pcie_intc3 1>,
869 <0 0 0 3 &pcie_intc3 2>,
870 <0 0 0 4 &pcie_intc3 3>;
871 #address-cells = <3>;
875 pcie_intc3: interrupt-controller {
876 #address-cells = <0>;
877 #interrupt-cells = <1>;
878 interrupt-controller;
882 pcie0: pcie@11300000 {
883 compatible = "mediatek,mt7988-pcie",
884 "mediatek,mt7986-pcie",
885 "mediatek,mt8192-pcie";
886 reg = <0 0x11300000 0 0x2000>;
887 reg-names = "pcie-mac";
888 ranges = <0x81000000 0x00 0x30000000 0x00
889 0x30000000 0x00 0x00200000>,
890 <0x82000000 0x00 0x30200000 0x00
891 0x30200000 0x00 0x07e00000>;
893 linux,pci-domain = <0>;
894 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
895 bus-range = <0x00 0xff>;
896 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
897 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
898 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
899 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
900 clock-names = "pl_250m", "tl_26m", "peri_26m",
902 pinctrl-names = "default";
903 pinctrl-0 = <&pcie0_pins>;
904 #interrupt-cells = <1>;
905 interrupt-map-mask = <0 0 0 0x7>;
906 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
907 <0 0 0 2 &pcie_intc0 1>,
908 <0 0 0 3 &pcie_intc0 2>,
909 <0 0 0 4 &pcie_intc0 3>;
910 #address-cells = <3>;
914 pcie_intc0: interrupt-controller {
915 #address-cells = <0>;
916 #interrupt-cells = <1>;
917 interrupt-controller;
921 pcie1: pcie@11310000 {
922 compatible = "mediatek,mt7988-pcie",
923 "mediatek,mt7986-pcie",
924 "mediatek,mt8192-pcie";
925 reg = <0 0x11310000 0 0x2000>;
926 reg-names = "pcie-mac";
927 ranges = <0x81000000 0x00 0x38000000 0x00
928 0x38000000 0x00 0x00200000>,
929 <0x82000000 0x00 0x38200000 0x00
930 0x38200000 0x00 0x07e00000>;
932 linux,pci-domain = <1>;
933 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
934 bus-range = <0x00 0xff>;
935 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
936 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
937 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
938 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
939 clock-names = "pl_250m", "tl_26m", "peri_26m",
941 pinctrl-names = "default";
942 pinctrl-0 = <&pcie1_pins>;
943 #interrupt-cells = <1>;
944 interrupt-map-mask = <0 0 0 0x7>;
945 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
946 <0 0 0 2 &pcie_intc1 1>,
947 <0 0 0 3 &pcie_intc1 2>,
948 <0 0 0 4 &pcie_intc1 3>;
949 #address-cells = <3>;
953 pcie_intc1: interrupt-controller {
954 #address-cells = <0>;
955 #interrupt-cells = <1>;
956 interrupt-controller;
960 tphy: tphy@11c50000 {
961 compatible = "mediatek,mt7988",
962 "mediatek,generic-tphy-v2";
964 #address-cells = <2>;
968 tphyu2port0: usb-phy@11c50000 {
969 reg = <0 0x11c50000 0 0x700>;
970 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
975 tphyu3port0: usb-phy@11c50700 {
976 reg = <0 0x11c50700 0 0x900>;
977 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
980 mediatek,usb3-pll-ssc-delta;
981 mediatek,usb3-pll-ssc-delta1;
985 topmisc: topmisc@11d10000 {
986 compatible = "mediatek,mt7988-topmisc", "syscon",
987 "mediatek,mt7988-power-controller";
988 reg = <0 0x11d10000 0 0x10000>;
990 #power-domain-cells = <1>;
991 #address-cells = <1>;
995 xphy: xphy@11e10000 {
996 compatible = "mediatek,mt7988",
999 #address-cells = <2>;
1001 status = "disabled";
1003 xphyu2port0: usb-phy@11e10000 {
1004 reg = <0 0x11e10000 0 0x400>;
1005 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1006 clock-names = "ref";
1010 xphyu3port0: usb-phy@11e13000 {
1011 reg = <0 0x11e13400 0 0x500>;
1012 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1013 clock-names = "ref";
1015 mediatek,syscon-type = <&topmisc 0x218 0>;
1019 xfi_pextp0: xfi-pextp@11f20000 {
1020 compatible = "mediatek,mt7988-xfi-pextp",
1021 "mediatek,mt7988-xfi-pextp_0",
1023 reg = <0 0x11f20000 0 0x10000>;
1027 xfi_pextp1: xfi-pextp@11f30000 {
1028 compatible = "mediatek,mt7988-xfi-pextp",
1029 "mediatek,mt7988-xfi-pextp_1",
1031 reg = <0 0x11f30000 0 0x10000>;
1035 xfi_pll: xfi-pll@11f40000 {
1036 compatible = "mediatek,mt7988-xfi-pll", "syscon";
1037 reg = <0 0x11f40000 0 0x1000>;
1041 efuse: efuse@11f50000 {
1042 compatible = "mediatek,efuse";
1043 reg = <0 0x11f50000 0 0x1000>;
1044 #address-cells = <1>;
1047 lvts_calibration: calib@918 {
1051 phy_calibration_p0: calib@940 {
1055 phy_calibration_p1: calib@954 {
1059 phy_calibration_p2: calib@968 {
1063 phy_calibration_p3: calib@97c {
1067 cpufreq_calibration: calib@278 {
1072 ethsys: syscon@15000000 {
1073 compatible = "mediatek,mt7988-ethsys", "syscon";
1074 reg = <0 0x15000000 0 0x1000>;
1077 #address-cells = <1>;
1081 switch: switch@15020000 {
1082 compatible = "mediatek,mt7988-switch";
1083 reg = <0 0x15020000 0 0x8000>;
1084 interrupt-controller;
1085 #interrupt-cells = <1>;
1086 interrupt-parent = <&gic>;
1087 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1088 resets = <ðrst 0>;
1089 #address-cells = <1>;
1093 #address-cells = <1>;
1099 phy-mode = "internal";
1100 phy-handle = <&gsw_phy0>;
1106 phy-mode = "internal";
1107 phy-handle = <&gsw_phy1>;
1113 phy-mode = "internal";
1114 phy-handle = <&gsw_phy2>;
1120 phy-mode = "internal";
1121 phy-handle = <&gsw_phy3>;
1126 ethernet = <&gmac0>;
1127 phy-mode = "internal";
1138 #address-cells = <1>;
1140 mediatek,pio = <&pio>;
1142 gsw_phy0: ethernet-phy@0 {
1143 compatible = "ethernet-phy-ieee802.3-c22";
1145 phy-mode = "internal";
1146 nvmem-cells = <&phy_calibration_p0>;
1147 nvmem-cell-names = "phy-cal-data";
1150 #address-cells = <1>;
1153 gsw_phy0_led0: gsw-phy0-led0@0 {
1155 function = LED_FUNCTION_LAN;
1156 status = "disabled";
1159 gsw_phy0_led1: gsw-phy0-led1@1 {
1161 function = LED_FUNCTION_LAN;
1162 status = "disabled";
1167 gsw_phy1: ethernet-phy@1 {
1168 compatible = "ethernet-phy-ieee802.3-c22";
1170 phy-mode = "internal";
1171 nvmem-cells = <&phy_calibration_p1>;
1172 nvmem-cell-names = "phy-cal-data";
1175 #address-cells = <1>;
1178 gsw_phy1_led0: gsw-phy1-led0@0 {
1180 function = LED_FUNCTION_LAN;
1181 status = "disabled";
1184 gsw_phy1_led1: gsw-phy1-led1@1 {
1186 function = LED_FUNCTION_LAN;
1187 status = "disabled";
1192 gsw_phy2: ethernet-phy@2 {
1193 compatible = "ethernet-phy-ieee802.3-c22";
1195 phy-mode = "internal";
1196 nvmem-cells = <&phy_calibration_p2>;
1197 nvmem-cell-names = "phy-cal-data";
1200 #address-cells = <1>;
1203 gsw_phy2_led0: gsw-phy2-led0@0 {
1205 function = LED_FUNCTION_LAN;
1206 status = "disabled";
1209 gsw_phy2_led1: gsw-phy2-led1@1 {
1211 function = LED_FUNCTION_LAN;
1212 status = "disabled";
1217 gsw_phy3: ethernet-phy@3 {
1218 compatible = "ethernet-phy-ieee802.3-c22";
1220 phy-mode = "internal";
1221 nvmem-cells = <&phy_calibration_p3>;
1222 nvmem-cell-names = "phy-cal-data";
1225 #address-cells = <1>;
1228 gsw_phy3_led0: gsw-phy3-led0@0 {
1230 function = LED_FUNCTION_LAN;
1231 status = "disabled";
1234 gsw_phy3_led1: gsw-phy3-led1@1 {
1236 function = LED_FUNCTION_LAN;
1237 status = "disabled";
1244 ethwarp: syscon@15031000 {
1245 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
1246 reg = <0 0x15031000 0 0x1000>;
1249 ethrst: reset-controller {
1250 compatible = "ti,syscon-reset";
1253 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
1258 eth: ethernet@15100000 {
1259 compatible = "mediatek,mt7988-eth";
1260 reg = <0 0x15100000 0 0x80000>,
1261 <0 0x15400000 0 0x380000>;
1262 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
1267 <ðsys CLK_ETHDMA_XGP2_EN>,
1268 <ðsys CLK_ETHDMA_XGP3_EN>,
1269 <ðsys CLK_ETHDMA_FE_EN>,
1270 <ðsys CLK_ETHDMA_GP2_EN>,
1271 <ðsys CLK_ETHDMA_GP1_EN>,
1272 <ðsys CLK_ETHDMA_GP3_EN>,
1273 <ðsys CLK_ETHDMA_ESW_EN>,
1274 <ðsys CLK_ETHDMA_CRYPT0_EN>,
1275 <&sgmiisys0 CLK_SGM0_TX_EN>,
1276 <&sgmiisys0 CLK_SGM0_RX_EN>,
1277 <&sgmiisys1 CLK_SGM1_TX_EN>,
1278 <&sgmiisys1 CLK_SGM1_RX_EN>,
1279 <ðwarp CLK_ETHWARP_WOCPU2_EN>,
1280 <ðwarp CLK_ETHWARP_WOCPU1_EN>,
1281 <ðwarp CLK_ETHWARP_WOCPU0_EN>,
1282 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1283 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1284 <&topckgen CLK_TOP_SGM_0_SEL>,
1285 <&topckgen CLK_TOP_SGM_1_SEL>,
1286 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
1287 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
1288 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1289 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1290 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1291 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1292 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1293 <&topckgen CLK_TOP_ETH_MII_SEL>,
1294 <&topckgen CLK_TOP_NETSYS_SEL>,
1295 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1296 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1297 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1298 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1299 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1300 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1301 "gp3", "esw", "crypto", "sgmii_tx250m",
1302 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
1303 "ethwarp_wocpu2", "ethwarp_wocpu1",
1304 "ethwarp_wocpu0", "top_usxgmii0_sel",
1305 "top_usxgmii1_sel", "top_sgm0_sel",
1306 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
1307 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
1308 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1309 "top_eth_sys_sel", "top_eth_xgmii_sel",
1310 "top_eth_mii_sel", "top_netsys_sel",
1311 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1312 "top_netsys_sync_250m_sel",
1313 "top_netsys_ppefb_250m_sel",
1314 "top_netsys_warp_sel";
1315 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1316 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1317 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1318 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1319 <&topckgen CLK_TOP_SGM_0_SEL>,
1320 <&topckgen CLK_TOP_SGM_1_SEL>;
1321 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1322 <&topckgen CLK_TOP_NET1PLL_D4>,
1323 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1324 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1325 <&apmixedsys CLK_APMIXED_SGMPLL>,
1326 <&apmixedsys CLK_APMIXED_SGMPLL>;
1327 mediatek,ethsys = <ðsys>;
1328 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
1329 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
1330 mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
1331 mediatek,xfi-pll = <&xfi_pll>;
1332 mediatek,infracfg = <&topmisc>;
1333 mediatek,toprgu = <&watchdog>;
1335 #address-cells = <1>;
1339 compatible = "mediatek,eth-mac";
1341 phy-mode = "internal";
1342 status = "disabled";
1352 compatible = "mediatek,eth-mac";
1354 status = "disabled";
1358 compatible = "mediatek,eth-mac";
1360 status = "disabled";
1363 mdio_bus: mdio-bus {
1364 #address-cells = <1>;
1367 /* internal 2.5G PHY */
1368 int_2p5g_phy: ethernet-phy@15 {
1369 compatible = "ethernet-phy-ieee802.3-c45";
1371 phy-mode = "internal";
1376 crypto: crypto@15600000 {
1377 compatible = "inside-secure,safexcel-eip197b";
1378 reg = <0 0x15600000 0 0x180000>;
1379 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1383 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1389 cpu_thermal: cpu-thermal {
1390 polling-delay-passive = <1000>;
1391 polling-delay = <1000>;
1392 thermal-sensors = <&lvts 0>;
1395 cpu_trip_crit: crit {
1396 temperature = <125000>;
1397 hysteresis = <2000>;
1402 temperature = <120000>;
1403 hysteresis = <2000>;
1407 cpu_trip_active_high: active-high {
1408 temperature = <115000>;
1409 hysteresis = <2000>;
1413 cpu_trip_active_med: active-med {
1414 temperature = <85000>;
1415 hysteresis = <2000>;
1419 cpu_trip_active_low: active-low {
1420 temperature = <40000>;
1421 hysteresis = <2000>;
1428 /* active: set fan to cooling level 2 */
1429 cooling-device = <&fan 3 3>;
1430 trip = <&cpu_trip_active_high>;
1434 /* active: set fan to cooling level 1 */
1435 cooling-device = <&fan 2 2>;
1436 trip = <&cpu_trip_active_med>;
1440 /* passive: set fan to cooling level 0 */
1441 cooling-device = <&fan 1 1>;
1442 trip = <&cpu_trip_active_low>;
1449 compatible = "arm,armv8-timer";
1450 interrupt-parent = <&gic>;
1451 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1452 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1453 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1454 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;