1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6 * Author: Jianhui Zhao <zhaojh329@gmail.com>
7 * Author: Daniel Golle <daniel@makrotopia.org>
10 #include <linux/clk-provider.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
19 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
21 static const struct mtk_gate_regs sgmii0_cg_regs
= {
27 #define GATE_SGMII0(_id, _name, _parent, _shift) { \
30 .parent_name = _parent, \
31 .regs = &sgmii0_cg_regs, \
33 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
36 static const struct mtk_gate sgmii0_clks
[] __initconst
= {
37 GATE_SGMII0(CLK_SGM0_TX_EN
, "sgm0_tx_en", "usb_tx250m", 2),
38 GATE_SGMII0(CLK_SGM0_RX_EN
, "sgm0_rx_en", "usb_eq_rx250m", 3),
39 GATE_SGMII0(CLK_SGM0_CK0_EN
, "sgm0_ck0_en", "usb_ln0", 4),
40 GATE_SGMII0(CLK_SGM0_CDR_CK0_EN
, "sgm0_cdr_ck0_en", "usb_cdr", 5),
43 static const struct mtk_gate_regs sgmii1_cg_regs
= {
49 #define GATE_SGMII1(_id, _name, _parent, _shift) { \
52 .parent_name = _parent, \
53 .regs = &sgmii1_cg_regs, \
55 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
58 static const struct mtk_gate sgmii1_clks
[] __initconst
= {
59 GATE_SGMII1(CLK_SGM1_TX_EN
, "sgm1_tx_en", "usb_tx250m", 2),
60 GATE_SGMII1(CLK_SGM1_RX_EN
, "sgm1_rx_en", "usb_eq_rx250m", 3),
61 GATE_SGMII1(CLK_SGM1_CK1_EN
, "sgm1_ck1_en", "usb_ln0", 4),
62 GATE_SGMII1(CLK_SGM1_CDR_CK1_EN
, "sgm1_cdr_ck1_en", "usb_cdr", 5),
65 static const struct mtk_gate_regs eth_cg_regs
= {
71 #define GATE_ETH(_id, _name, _parent, _shift) { \
74 .parent_name = _parent, \
75 .regs = ð_cg_regs, \
77 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
80 static const struct mtk_gate eth_clks
[] __initconst
= {
81 GATE_ETH(CLK_ETH_FE_EN
, "eth_fe_en", "netsys_2x", 6),
82 GATE_ETH(CLK_ETH_GP2_EN
, "eth_gp2_en", "sgm_325m", 7),
83 GATE_ETH(CLK_ETH_GP1_EN
, "eth_gp1_en", "sgm_325m", 8),
84 GATE_ETH(CLK_ETH_WOCPU0_EN
, "eth_wocpu0_en", "netsys_wed_mcu", 15),
87 static void __init
mtk_sgmiisys_0_init(struct device_node
*node
)
89 struct clk_onecell_data
*clk_data
;
92 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks
));
94 mtk_clk_register_gates(node
, sgmii0_clks
, ARRAY_SIZE(sgmii0_clks
),
97 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
99 pr_err("%s(): could not register clock provider: %d\n",
102 CLK_OF_DECLARE(mtk_sgmiisys_0
, "mediatek,mt7981-sgmiisys_0",
103 mtk_sgmiisys_0_init
);
105 static void __init
mtk_sgmiisys_1_init(struct device_node
*node
)
107 struct clk_onecell_data
*clk_data
;
110 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks
));
112 mtk_clk_register_gates(node
, sgmii1_clks
, ARRAY_SIZE(sgmii1_clks
),
115 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
118 pr_err("%s(): could not register clock provider: %d\n",
121 CLK_OF_DECLARE(mtk_sgmiisys_1
, "mediatek,mt7981-sgmiisys_1",
122 mtk_sgmiisys_1_init
);
124 static void __init
mtk_ethsys_init(struct device_node
*node
)
126 struct clk_onecell_data
*clk_data
;
129 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(eth_clks
));
131 mtk_clk_register_gates(node
, eth_clks
, ARRAY_SIZE(eth_clks
), clk_data
);
133 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
136 pr_err("%s(): could not register clock provider: %d\n",
139 CLK_OF_DECLARE(mtk_ethsys
, "mediatek,mt7981-ethsys", mtk_ethsys_init
);