1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
8 #include <linux/clk-provider.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
17 #include <dt-bindings/clock/mt7986-clk.h>
19 static const struct mtk_gate_regs sgmii0_cg_regs
= {
25 #define GATE_SGMII0(_id, _name, _parent, _shift) \
27 .id = _id, .name = _name, .parent_name = _parent, \
28 .regs = &sgmii0_cg_regs, .shift = _shift, \
29 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
32 static const struct mtk_gate sgmii0_clks
[] __initconst
= {
33 GATE_SGMII0(CLK_SGMII0_TX250M_EN
, "sgmii0_tx250m_en", "top_xtal", 2),
34 GATE_SGMII0(CLK_SGMII0_RX250M_EN
, "sgmii0_rx250m_en", "top_xtal", 3),
35 GATE_SGMII0(CLK_SGMII0_CDR_REF
, "sgmii0_cdr_ref", "top_xtal", 4),
36 GATE_SGMII0(CLK_SGMII0_CDR_FB
, "sgmii0_cdr_fb", "top_xtal", 5),
39 static const struct mtk_gate_regs sgmii1_cg_regs
= {
45 #define GATE_SGMII1(_id, _name, _parent, _shift) \
47 .id = _id, .name = _name, .parent_name = _parent, \
48 .regs = &sgmii1_cg_regs, .shift = _shift, \
49 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
52 static const struct mtk_gate sgmii1_clks
[] __initconst
= {
53 GATE_SGMII1(CLK_SGMII1_TX250M_EN
, "sgmii1_tx250m_en", "top_xtal", 2),
54 GATE_SGMII1(CLK_SGMII1_RX250M_EN
, "sgmii1_rx250m_en", "top_xtal", 3),
55 GATE_SGMII1(CLK_SGMII1_CDR_REF
, "sgmii1_cdr_ref", "top_xtal", 4),
56 GATE_SGMII1(CLK_SGMII1_CDR_FB
, "sgmii1_cdr_fb", "top_xtal", 5),
59 static const struct mtk_gate_regs eth_cg_regs
= {
65 #define GATE_ETH(_id, _name, _parent, _shift) \
67 .id = _id, .name = _name, .parent_name = _parent, \
68 .regs = ð_cg_regs, .shift = _shift, \
69 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
72 static const struct mtk_gate eth_clks
[] __initconst
= {
73 GATE_ETH(CLK_ETH_FE_EN
, "eth_fe_en", "netsys_2x_sel", 6),
74 GATE_ETH(CLK_ETH_GP2_EN
, "eth_gp2_en", "sgm_325m_sel", 7),
75 GATE_ETH(CLK_ETH_GP1_EN
, "eth_gp1_en", "sgm_325m_sel", 8),
76 GATE_ETH(CLK_ETH_WOCPU1_EN
, "eth_wocpu1_en", "netsys_mcu_sel", 14),
77 GATE_ETH(CLK_ETH_WOCPU0_EN
, "eth_wocpu0_en", "netsys_mcu_sel", 15),
80 static void __init
mtk_sgmiisys_0_init(struct device_node
*node
)
82 struct clk_onecell_data
*clk_data
;
85 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks
));
87 mtk_clk_register_gates(node
, sgmii0_clks
, ARRAY_SIZE(sgmii0_clks
),
90 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
92 pr_err("%s(): could not register clock provider: %d\n",
95 CLK_OF_DECLARE(mtk_sgmiisys_0
, "mediatek,mt7986-sgmiisys_0",
98 static void __init
mtk_sgmiisys_1_init(struct device_node
*node
)
100 struct clk_onecell_data
*clk_data
;
103 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks
));
105 mtk_clk_register_gates(node
, sgmii1_clks
, ARRAY_SIZE(sgmii1_clks
),
108 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
111 pr_err("%s(): could not register clock provider: %d\n",
114 CLK_OF_DECLARE(mtk_sgmiisys_1
, "mediatek,mt7986-sgmiisys_1",
115 mtk_sgmiisys_1_init
);
117 static void __init
mtk_ethsys_init(struct device_node
*node
)
119 struct clk_onecell_data
*clk_data
;
122 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(eth_clks
));
124 mtk_clk_register_gates(node
, eth_clks
, ARRAY_SIZE(eth_clks
), clk_data
);
126 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
129 pr_err("%s(): could not register clock provider: %d\n",
132 CLK_OF_DECLARE(mtk_ethsys
, "mediatek,mt7986-ethsys", mtk_ethsys_init
);