1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
8 #include <linux/clk-provider.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
15 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
17 static const struct mtk_gate_regs ethdma_cg_regs
= {
23 #define GATE_ETHDMA(_id, _name, _parent, _shift) \
25 .id = _id, .name = _name, .parent_name = _parent, \
26 .regs = ðdma_cg_regs, .shift = _shift, \
27 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
30 static const struct mtk_gate ethdma_clks
[] = {
31 GATE_ETHDMA(CLK_ETHDMA_XGP1_EN
, "ethdma_xgp1_en", "top_xtal", 0),
32 GATE_ETHDMA(CLK_ETHDMA_XGP2_EN
, "ethdma_xgp2_en", "top_xtal", 1),
33 GATE_ETHDMA(CLK_ETHDMA_XGP3_EN
, "ethdma_xgp3_en", "top_xtal", 2),
34 GATE_ETHDMA(CLK_ETHDMA_FE_EN
, "ethdma_fe_en", "netsys_2x_sel", 6),
35 GATE_ETHDMA(CLK_ETHDMA_GP2_EN
, "ethdma_gp2_en", "top_xtal", 7),
36 GATE_ETHDMA(CLK_ETHDMA_GP1_EN
, "ethdma_gp1_en", "top_xtal", 8),
37 GATE_ETHDMA(CLK_ETHDMA_GP3_EN
, "ethdma_gp3_en", "top_xtal", 10),
38 GATE_ETHDMA(CLK_ETHDMA_ESW_EN
, "ethdma_esw_en", "netsys_gsw_sel", 16),
39 GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN
, "ethdma_crypt0_en", "eip197_sel",
43 static int clk_mt7988_ethsys_probe(struct platform_device
*pdev
)
45 struct clk_onecell_data
*clk_data
;
46 struct device_node
*node
= pdev
->dev
.of_node
;
50 base
= of_iomap(node
, 0);
52 pr_err("%s(): ioremap failed\n", __func__
);
56 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks
));
61 mtk_clk_register_gates(node
, ethdma_clks
, ARRAY_SIZE(ethdma_clks
),
64 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
66 pr_err("%s(): could not register clock provider: %d\n",
73 mtk_free_clk_data(clk_data
);
77 static const struct mtk_gate_regs sgmii0_cg_regs
= {
83 #define GATE_SGMII0(_id, _name, _parent, _shift) \
85 .id = _id, .name = _name, .parent_name = _parent, \
86 .regs = &sgmii0_cg_regs, .shift = _shift, \
87 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
90 static const struct mtk_gate sgmii0_clks
[] = {
91 GATE_SGMII0(CLK_SGM0_TX_EN
, "sgm0_tx_en", "top_xtal", 2),
92 GATE_SGMII0(CLK_SGM0_RX_EN
, "sgm0_rx_en", "top_xtal", 3),
95 static int clk_mt7988_sgmii0_probe(struct platform_device
*pdev
)
97 struct clk_onecell_data
*clk_data
;
98 struct device_node
*node
= pdev
->dev
.of_node
;
102 base
= of_iomap(node
, 0);
104 pr_err("%s(): ioremap failed\n", __func__
);
108 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks
));
113 mtk_clk_register_gates(node
, sgmii0_clks
, ARRAY_SIZE(sgmii0_clks
),
116 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
118 pr_err("%s(): could not register clock provider: %d\n",
125 mtk_free_clk_data(clk_data
);
129 static const struct mtk_gate_regs sgmii1_cg_regs
= {
135 #define GATE_SGMII1(_id, _name, _parent, _shift) \
137 .id = _id, .name = _name, .parent_name = _parent, \
138 .regs = &sgmii1_cg_regs, .shift = _shift, \
139 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
142 static const struct mtk_gate sgmii1_clks
[] = {
143 GATE_SGMII1(CLK_SGM1_TX_EN
, "sgm1_tx_en", "top_xtal", 2),
144 GATE_SGMII1(CLK_SGM1_RX_EN
, "sgm1_rx_en", "top_xtal", 3),
147 static int clk_mt7988_sgmii1_probe(struct platform_device
*pdev
)
149 struct clk_onecell_data
*clk_data
;
150 struct device_node
*node
= pdev
->dev
.of_node
;
154 base
= of_iomap(node
, 0);
156 pr_err("%s(): ioremap failed\n", __func__
);
160 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks
));
165 mtk_clk_register_gates(node
, sgmii1_clks
, ARRAY_SIZE(sgmii1_clks
),
168 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
170 pr_err("%s(): could not register clock provider: %d\n",
177 mtk_free_clk_data(clk_data
);
181 static const struct mtk_gate_regs ethwarp_cg_regs
= {
187 #define GATE_ETHWARP(_id, _name, _parent, _shift) \
189 .id = _id, .name = _name, .parent_name = _parent, \
190 .regs = ðwarp_cg_regs, .shift = _shift, \
191 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
194 static const struct mtk_gate ethwarp_clks
[] = {
195 GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN
, "ethwarp_wocpu2_en",
196 "netsys_mcu_sel", 13),
197 GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN
, "ethwarp_wocpu1_en",
198 "netsys_mcu_sel", 14),
199 GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN
, "ethwarp_wocpu0_en",
200 "netsys_mcu_sel", 15),
203 static int clk_mt7988_ethwarp_probe(struct platform_device
*pdev
)
205 struct clk_onecell_data
*clk_data
;
206 struct device_node
*node
= pdev
->dev
.of_node
;
210 base
= of_iomap(node
, 0);
212 pr_err("%s(): ioremap failed\n", __func__
);
216 clk_data
= mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks
));
221 mtk_clk_register_gates(node
, ethwarp_clks
, ARRAY_SIZE(ethwarp_clks
),
224 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
226 pr_err("%s(): could not register clock provider: %d\n",
233 mtk_free_clk_data(clk_data
);
237 static const struct of_device_id of_match_clk_mt7988_ethsys
[] = {
239 .compatible
= "mediatek,mt7988-ethsys",
244 static struct platform_driver clk_mt7988_ethsys_drv
= {
245 .probe
= clk_mt7988_ethsys_probe
,
247 .name
= "clk-mt7988-ethsys",
248 .of_match_table
= of_match_clk_mt7988_ethsys
,
251 builtin_platform_driver(clk_mt7988_ethsys_drv
);
253 static const struct of_device_id of_match_clk_mt7988_sgmii0
[] = {
255 .compatible
= "mediatek,mt7988-sgmiisys_0",
260 static struct platform_driver clk_mt7988_sgmii0_drv
= {
261 .probe
= clk_mt7988_sgmii0_probe
,
263 .name
= "clk-mt7988-sgmiisys_0",
264 .of_match_table
= of_match_clk_mt7988_sgmii0
,
267 builtin_platform_driver(clk_mt7988_sgmii0_drv
);
269 static const struct of_device_id of_match_clk_mt7988_sgmii1
[] = {
271 .compatible
= "mediatek,mt7988-sgmiisys_1",
276 static struct platform_driver clk_mt7988_sgmii1_drv
= {
277 .probe
= clk_mt7988_sgmii1_probe
,
279 .name
= "clk-mt7988-sgmiisys_1",
280 .of_match_table
= of_match_clk_mt7988_sgmii1
,
283 builtin_platform_driver(clk_mt7988_sgmii1_drv
);
285 static const struct of_device_id of_match_clk_mt7988_ethwarp
[] = {
287 .compatible
= "mediatek,mt7988-ethwarp",
292 static struct platform_driver clk_mt7988_ethwarp_drv
= {
293 .probe
= clk_mt7988_ethwarp_probe
,
295 .name
= "clk-mt7988-ethwarp",
296 .of_match_table
= of_match_clk_mt7988_ethwarp
,
299 builtin_platform_driver(clk_mt7988_ethwarp_drv
);