2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
12 #include "mt7622.dtsi"
13 #include "mt6380.dtsi"
16 model = "MT7622_MT7531 RFB";
17 compatible = "mediatek,mt7622,ubi";
24 stdout-path = "serial0:115200n8";
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
36 sram-supply = <&mt6380_vm_reg>;
41 compatible = "gpio-keys";
46 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
51 linux,code = <KEY_WPS_BUTTON>;
52 gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
57 compatible = "mediatek,mt753x";
58 mediatek,ethsys = <ðsys>;
64 compatible = "gpio-leds";
67 label = "bpi-r64:pio:green";
68 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
72 label = "bpi-r64:pio:red";
73 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
78 reg = <0 0x40000000 0 0x40000000>;
81 reg_1p8v: regulator-1p8v {
82 compatible = "regulator-fixed";
83 regulator-name = "fixed-1.8V";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
89 reg_3p3v: regulator-3p3v {
90 compatible = "regulator-fixed";
91 regulator-name = "fixed-3.3V";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
98 reg_5v: regulator-5v {
99 compatible = "regulator-fixed";
100 regulator-name = "fixed-5V";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&irrx_pins>;
125 compatible = "mediatek,eth-mac";
127 phy-mode = "2500base-x";
137 compatible = "mediatek,eth-mac";
149 #address-cells = <1>;
155 mediatek,mdio = <&mdio>;
156 mediatek,portmap = "llllw";
157 mediatek,mdio_master_pinmux = <0>;
158 reset-gpios = <&pio 54 0>;
159 interrupt-parent = <&pio>;
160 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
164 compatible = "mediatek,mt753x-port";
174 compatible = "mediatek,mt753x-port";
185 pinctrl-names = "default";
186 pinctrl-0 = <&i2c1_pins>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&i2c2_pins>;
197 pinctrl-names = "default", "state_uhs";
198 pinctrl-0 = <&emmc_pins_default>;
199 pinctrl-1 = <&emmc_pins_uhs>;
202 max-frequency = <50000000>;
205 vmmc-supply = <®_3p3v>;
206 vqmmc-supply = <®_1p8v>;
207 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
208 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
213 pinctrl-names = "default", "state_uhs";
214 pinctrl-0 = <&sd0_pins_default>;
215 pinctrl-1 = <&sd0_pins_uhs>;
218 max-frequency = <50000000>;
221 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
222 vmmc-supply = <®_3p3v>;
223 vqmmc-supply = <®_3p3v>;
224 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
225 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
229 pinctrl-names = "default";
230 pinctrl-0 = <¶llel_nand_pins>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&spi_nor_pins>;
240 compatible = "jedec,spi-nor";
246 pinctrl-names = "default";
247 pinctrl-0 = <&pcie0_pins>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pcie1_pins>;
258 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
259 * SATA functions. i.e. output-high: PCIe, output-low: SATA
263 gpios = <90 GPIO_ACTIVE_HIGH>;
267 /* eMMC is shared pin with parallel NAND */
268 emmc_pins_default: emmc-pins-default {
270 function = "emmc", "emmc_rst";
274 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
275 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
276 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
279 pins = "NDL0", "NDL1", "NDL2",
280 "NDL3", "NDL4", "NDL5",
281 "NDL6", "NDL7", "NRB";
292 emmc_pins_uhs: emmc-pins-uhs {
299 pins = "NDL0", "NDL1", "NDL2",
300 "NDL3", "NDL4", "NDL5",
301 "NDL6", "NDL7", "NRB";
303 drive-strength = <4>;
309 drive-strength = <4>;
317 groups = "mdc_mdio", "rgmii_via_gmac2";
321 i2c1_pins: i2c1-pins {
328 i2c2_pins: i2c2-pins {
335 i2s1_pins: i2s1-pins {
338 groups = "i2s_out_mclk_bclk_ws",
344 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
345 "I2S_WS", "I2S_MCLK";
346 drive-strength = <12>;
351 irrx_pins: irrx-pins {
358 irtx_pins: irtx-pins {
365 /* Parallel nand is shared pin with eMMC */
366 parallel_nand_pins: parallel-nand-pins {
373 pcie0_pins: pcie0-pins {
376 groups = "pcie0_pad_perst",
382 pcie1_pins: pcie1-pins {
385 groups = "pcie1_pad_perst",
391 pmic_bus_pins: pmic-bus-pins {
398 pwm7_pins: pwm1-2-pins {
401 groups = "pwm_ch7_2";
405 wled_pins: wled-pins {
412 sd0_pins_default: sd0-pins-default {
418 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
419 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
420 * DAT2, DAT3, CMD, CLK for SD respectively.
423 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
424 "I2S2_IN","I2S4_OUT";
426 drive-strength = <8>;
431 drive-strength = <12>;
440 sd0_pins_uhs: sd0-pins-uhs {
447 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
448 "I2S2_IN","I2S4_OUT";
459 /* Serial NAND is shared pin with SPI-NOR */
460 serial_nand_pins: serial-nand-pins {
467 spic0_pins: spic0-pins {
474 spic1_pins: spic1-pins {
481 /* SPI-NOR is shared pin with serial NAND */
482 spi_nor_pins: spi-nor-pins {
489 /* serial NAND is shared pin with SPI-NOR */
490 serial_nand_pins: serial-nand-pins {
497 uart0_pins: uart0-pins {
500 groups = "uart0_0_tx_rx" ;
504 uart2_pins: uart2-pins {
507 groups = "uart2_1_tx_rx" ;
511 watchdog_pins: watchdog-pins {
513 function = "watchdog";
520 pinctrl-names = "default";
521 pinctrl-0 = <&pwm7_pins>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&pmic_bus_pins>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&serial_nand_pins>;
546 #address-cells = <1>;
548 compatible = "spi-nand";
549 spi-max-frequency = <104000000>;
553 compatible = "fixed-partitions";
554 #address-cells = <1>;
559 reg = <0x00000 0x0080000>;
565 reg = <0x80000 0x0040000>;
569 label = "Bootloader";
570 reg = <0xc0000 0x0080000>;
575 reg = <0x140000 0x0080000>;
578 factory: partition@1c0000 {
580 reg = <0x1c0000 0x0040000>;
585 reg = <0x200000 0x400000>;
590 reg = <0x600000 0x1C00000>;
595 reg = <0x2200000 0x4000000>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&spic0_pins>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&spic1_pins>;
614 vusb33-supply = <®_3p3v>;
615 vbus-supply = <®_5v>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&uart0_pins>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&uart2_pins>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&watchdog_pins>;
642 mediatek,mtd-eeprom = <&factory 0x0000>;