target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 #include "mt7622.dtsi"
  13 #include "mt6380.dtsi"
  14
  15 / {
  16         model = "MT7622_MT7531 RFB";
  17         compatible = "mediatek,mt7622,ubi";
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 factory {
  44                         label = "factory";
  45                         linux,code = <BTN_0>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
  53                 };
  54         };
  55
  56         gsw: gsw@0 {
  57                 compatible = "mediatek,mt753x";
  58                 mediatek,ethsys = <&ethsys>;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61         };
  62
  63         leds {
  64                 compatible = "gpio-leds";
  65
  66                 green {
  67                         label = "bpi-r64:pio:green";
  68                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  69                 };
  70
  71                 red {
  72                         label = "bpi-r64:pio:red";
  73                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  74                 };
  75         };
  76
  77         memory {
  78                 reg = <0 0x40000000 0 0x40000000>;
  79         };
  80
  81         reg_1p8v: regulator-1p8v {
  82                 compatible = "regulator-fixed";
  83                 regulator-name = "fixed-1.8V";
  84                 regulator-min-microvolt = <1800000>;
  85                 regulator-max-microvolt = <1800000>;
  86                 regulator-always-on;
  87         };
  88
  89         reg_3p3v: regulator-3p3v {
  90                 compatible = "regulator-fixed";
  91                 regulator-name = "fixed-3.3V";
  92                 regulator-min-microvolt = <3300000>;
  93                 regulator-max-microvolt = <3300000>;
  94                 regulator-boot-on;
  95                 regulator-always-on;
  96         };
  97
  98         reg_5v: regulator-5v {
  99                 compatible = "regulator-fixed";
 100                 regulator-name = "fixed-5V";
 101                 regulator-min-microvolt = <5000000>;
 102                 regulator-max-microvolt = <5000000>;
 103                 regulator-boot-on;
 104                 regulator-always-on;
 105         };
 106 };
 107
 108 &bch {
 109         status = "okay";
 110 };
 111
 112 &btif {
 113         status = "okay";
 114 };
 115
 116 &cir {
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&irrx_pins>;
 119         status = "okay";
 120 };
 121
 122 &eth {
 123         status = "okay";
 124         gmac0: mac@0 {
 125                 compatible = "mediatek,eth-mac";
 126                 reg = <0>;
 127                 phy-mode = "2500base-x";
 128
 129                 fixed-link {
 130                         speed = <2500>;
 131                         full-duplex;
 132                         pause;
 133                 };
 134         };
 135
 136         gmac1: mac@1 {
 137                 compatible = "mediatek,eth-mac";
 138                 reg = <1>;
 139                 phy-mode = "rgmii";
 140
 141                 fixed-link {
 142                         speed = <1000>;
 143                         full-duplex;
 144                         pause;
 145                 };
 146         };
 147
 148         mdio: mdio-bus {
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151         };
 152 };
 153
 154 &gsw {
 155         mediatek,mdio = <&mdio>;
 156         mediatek,portmap = "llllw";
 157         mediatek,mdio_master_pinmux = <0>;
 158         reset-gpios = <&pio 54 0>;
 159         interrupt-parent = <&pio>;
 160         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 161         status = "okay";
 162
 163         port5: port@5 {
 164                 compatible = "mediatek,mt753x-port";
 165                 reg = <5>;
 166                 phy-mode = "rgmii";
 167                 fixed-link {
 168                         speed = <1000>;
 169                         full-duplex;
 170                 };
 171         };
 172
 173         port6: port@6 {
 174                 compatible = "mediatek,mt753x-port";
 175                 reg = <6>;
 176                 phy-mode = "sgmii";
 177                 fixed-link {
 178                         speed = <2500>;
 179                         full-duplex;
 180                 };
 181         };
 182 };
 183
 184 &i2c1 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&i2c1_pins>;
 187         status = "okay";
 188 };
 189
 190 &i2c2 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&i2c2_pins>;
 193         status = "okay";
 194 };
 195
 196 &mmc0 {
 197         pinctrl-names = "default", "state_uhs";
 198         pinctrl-0 = <&emmc_pins_default>;
 199         pinctrl-1 = <&emmc_pins_uhs>;
 200         status = "okay";
 201         bus-width = <8>;
 202         max-frequency = <50000000>;
 203         cap-mmc-highspeed;
 204         mmc-hs200-1_8v;
 205         vmmc-supply = <&reg_3p3v>;
 206         vqmmc-supply = <&reg_1p8v>;
 207         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 208         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 209         non-removable;
 210 };
 211
 212 &mmc1 {
 213         pinctrl-names = "default", "state_uhs";
 214         pinctrl-0 = <&sd0_pins_default>;
 215         pinctrl-1 = <&sd0_pins_uhs>;
 216         status = "okay";
 217         bus-width = <4>;
 218         max-frequency = <50000000>;
 219         cap-sd-highspeed;
 220         r_smpl = <1>;
 221         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 222         vmmc-supply = <&reg_3p3v>;
 223         vqmmc-supply = <&reg_3p3v>;
 224         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 225         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 226 };
 227
 228 &nandc {
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&parallel_nand_pins>;
 231         status = "disabled";
 232 };
 233
 234 &nor_flash {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&spi_nor_pins>;
 237         status = "disabled";
 238
 239         flash@0 {
 240                 compatible = "jedec,spi-nor";
 241                 reg = <0>;
 242         };
 243 };
 244
 245 &pcie0 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pcie0_pins>;
 248         status = "okay";
 249 };
 250
 251 &pcie1 {
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pcie1_pins>;
 254         status = "okay";
 255 };
 256
 257 &pio {
 258         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 259          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 260          */
 261         asm_sel {
 262                 gpio-hog;
 263                 gpios = <90 GPIO_ACTIVE_HIGH>;
 264                 output-high;
 265         };
 266
 267         /* eMMC is shared pin with parallel NAND */
 268         emmc_pins_default: emmc-pins-default {
 269                 mux {
 270                         function = "emmc", "emmc_rst";
 271                         groups = "emmc";
 272                 };
 273
 274                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 275                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 276                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 277                  */
 278                 conf-cmd-dat {
 279                         pins = "NDL0", "NDL1", "NDL2",
 280                                "NDL3", "NDL4", "NDL5",
 281                                "NDL6", "NDL7", "NRB";
 282                         input-enable;
 283                         bias-pull-up;
 284                 };
 285
 286                 conf-clk {
 287                         pins = "NCLE";
 288                         bias-pull-down;
 289                 };
 290         };
 291
 292         emmc_pins_uhs: emmc-pins-uhs {
 293                 mux {
 294                         function = "emmc";
 295                         groups = "emmc";
 296                 };
 297
 298                 conf-cmd-dat {
 299                         pins = "NDL0", "NDL1", "NDL2",
 300                                "NDL3", "NDL4", "NDL5",
 301                                "NDL6", "NDL7", "NRB";
 302                         input-enable;
 303                         drive-strength = <4>;
 304                         bias-pull-up;
 305                 };
 306
 307                 conf-clk {
 308                         pins = "NCLE";
 309                         drive-strength = <4>;
 310                         bias-pull-down;
 311                 };
 312         };
 313
 314         eth_pins: eth-pins {
 315                 mux {
 316                         function = "eth";
 317                         groups = "mdc_mdio", "rgmii_via_gmac2";
 318                 };
 319         };
 320
 321         i2c1_pins: i2c1-pins {
 322                 mux {
 323                         function = "i2c";
 324                         groups =  "i2c1_0";
 325                 };
 326         };
 327
 328         i2c2_pins: i2c2-pins {
 329                 mux {
 330                         function = "i2c";
 331                         groups =  "i2c2_0";
 332                 };
 333         };
 334
 335         i2s1_pins: i2s1-pins {
 336                 mux {
 337                         function = "i2s";
 338                         groups =  "i2s_out_mclk_bclk_ws",
 339                                   "i2s1_in_data",
 340                                   "i2s1_out_data";
 341                 };
 342
 343                 conf {
 344                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 345                                "I2S_WS", "I2S_MCLK";
 346                         drive-strength = <12>;
 347                         bias-pull-down;
 348                 };
 349         };
 350
 351         irrx_pins: irrx-pins {
 352                 mux {
 353                         function = "ir";
 354                         groups =  "ir_1_rx";
 355                 };
 356         };
 357
 358         irtx_pins: irtx-pins {
 359                 mux {
 360                         function = "ir";
 361                         groups =  "ir_1_tx";
 362                 };
 363         };
 364
 365         /* Parallel nand is shared pin with eMMC */
 366         parallel_nand_pins: parallel-nand-pins {
 367                 mux {
 368                         function = "flash";
 369                         groups = "par_nand";
 370                 };
 371         };
 372
 373         pcie0_pins: pcie0-pins {
 374                 mux {
 375                         function = "pcie";
 376                         groups = "pcie0_pad_perst",
 377                                  "pcie0_1_waken",
 378                                  "pcie0_1_clkreq";
 379                 };
 380         };
 381
 382         pcie1_pins: pcie1-pins {
 383                 mux {
 384                         function = "pcie";
 385                         groups = "pcie1_pad_perst",
 386                                  "pcie1_0_waken",
 387                                  "pcie1_0_clkreq";
 388                 };
 389         };
 390
 391         pmic_bus_pins: pmic-bus-pins {
 392                 mux {
 393                         function = "pmic";
 394                         groups = "pmic_bus";
 395                 };
 396         };
 397
 398         pwm7_pins: pwm1-2-pins {
 399                 mux {
 400                         function = "pwm";
 401                         groups = "pwm_ch7_2";
 402                 };
 403         };
 404
 405         wled_pins: wled-pins {
 406                 mux {
 407                         function = "led";
 408                         groups = "wled";
 409                 };
 410         };
 411
 412         sd0_pins_default: sd0-pins-default {
 413                 mux {
 414                         function = "sd";
 415                         groups = "sd_0";
 416                 };
 417
 418                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 419                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 420                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 421                  */
 422                 conf-cmd-data {
 423                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 424                                "I2S2_IN","I2S4_OUT";
 425                         input-enable;
 426                         drive-strength = <8>;
 427                         bias-pull-up;
 428                 };
 429                 conf-clk {
 430                         pins = "I2S3_OUT";
 431                         drive-strength = <12>;
 432                         bias-pull-down;
 433                 };
 434                 conf-cd {
 435                         pins = "TXD3";
 436                         bias-pull-up;
 437                 };
 438         };
 439
 440         sd0_pins_uhs: sd0-pins-uhs {
 441                 mux {
 442                         function = "sd";
 443                         groups = "sd_0";
 444                 };
 445
 446                 conf-cmd-data {
 447                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 448                                "I2S2_IN","I2S4_OUT";
 449                         input-enable;
 450                         bias-pull-up;
 451                 };
 452
 453                 conf-clk {
 454                         pins = "I2S3_OUT";
 455                         bias-pull-down;
 456                 };
 457         };
 458
 459         /* Serial NAND is shared pin with SPI-NOR */
 460         serial_nand_pins: serial-nand-pins {
 461                 mux {
 462                         function = "flash";
 463                         groups = "snfi";
 464                 };
 465         };
 466
 467         spic0_pins: spic0-pins {
 468                 mux {
 469                         function = "spi";
 470                         groups = "spic0_0";
 471                 };
 472         };
 473
 474         spic1_pins: spic1-pins {
 475                 mux {
 476                         function = "spi";
 477                         groups = "spic1_0";
 478                 };
 479         };
 480
 481         /* SPI-NOR is shared pin with serial NAND */
 482         spi_nor_pins: spi-nor-pins {
 483                 mux {
 484                         function = "flash";
 485                         groups = "spi_nor";
 486                 };
 487         };
 488
 489         /* serial NAND is shared pin with SPI-NOR */
 490         serial_nand_pins: serial-nand-pins {
 491                 mux {
 492                         function = "flash";
 493                         groups = "snfi";
 494                 };
 495         };
 496
 497         uart0_pins: uart0-pins {
 498                 mux {
 499                         function = "uart";
 500                         groups = "uart0_0_tx_rx" ;
 501                 };
 502         };
 503
 504         uart2_pins: uart2-pins {
 505                 mux {
 506                         function = "uart";
 507                         groups = "uart2_1_tx_rx" ;
 508                 };
 509         };
 510
 511         watchdog_pins: watchdog-pins {
 512                 mux {
 513                         function = "watchdog";
 514                         groups = "watchdog";
 515                 };
 516         };
 517 };
 518
 519 &pwm {
 520         pinctrl-names = "default";
 521         pinctrl-0 = <&pwm7_pins>;
 522         status = "okay";
 523 };
 524
 525 &pwrap {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&pmic_bus_pins>;
 528
 529         status = "okay";
 530 };
 531
 532 &sata {
 533         status = "disable";
 534 };
 535
 536 &sata_phy {
 537         status = "disable";
 538 };
 539
 540 &snfi {
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&serial_nand_pins>;
 543         status = "okay";
 544
 545         spi_nand@0 {
 546                 #address-cells = <1>;
 547                 #size-cells = <1>;
 548                 compatible = "spi-nand";
 549                 spi-max-frequency = <104000000>;
 550                 reg = <0>;
 551
 552                 partitions {
 553                         compatible = "fixed-partitions";
 554                         #address-cells = <1>;
 555                         #size-cells = <1>;
 556
 557                         partition@0 {
 558                                 label = "Preloader";
 559                                 reg = <0x00000 0x0080000>;
 560                                 read-only;
 561                         };
 562
 563                         partition@80000 {
 564                                 label = "ATF";
 565                                 reg = <0x80000 0x0040000>;
 566                         };
 567
 568                         partition@c0000 {
 569                                 label = "Bootloader";
 570                                 reg = <0xc0000 0x0080000>;
 571                         };
 572
 573                         partition@140000 {
 574                                 label = "Config";
 575                                 reg = <0x140000 0x0080000>;
 576                         };
 577
 578                         factory: partition@1c0000 {
 579                                 label = "Factory";
 580                                 reg = <0x1c0000 0x0040000>;
 581                         };
 582
 583                         partition@200000 {
 584                                 label = "kernel";
 585                                 reg = <0x200000 0x400000>;
 586                         };
 587
 588                         partition@600000 {
 589                                 label = "ubi";
 590                                 reg = <0x600000 0x1C00000>;
 591                         };
 592
 593                         partition@2200000 {
 594                                 label = "User_data";
 595                                 reg = <0x2200000 0x4000000>;
 596                         };
 597                 };
 598         };
 599 };
 600
 601 &spi0 {
 602         pinctrl-names = "default";
 603         pinctrl-0 = <&spic0_pins>;
 604         status = "okay";
 605 };
 606
 607 &spi1 {
 608         pinctrl-names = "default";
 609         pinctrl-0 = <&spic1_pins>;
 610         status = "okay";
 611 };
 612
 613 &ssusb {
 614         vusb33-supply = <&reg_3p3v>;
 615         vbus-supply = <&reg_5v>;
 616         status = "okay";
 617 };
 618
 619 &u3phy {
 620         status = "okay";
 621 };
 622
 623 &uart0 {
 624         pinctrl-names = "default";
 625         pinctrl-0 = <&uart0_pins>;
 626         status = "okay";
 627 };
 628
 629 &uart2 {
 630         pinctrl-names = "default";
 631         pinctrl-0 = <&uart2_pins>;
 632         status = "okay";
 633 };
 634
 635 &watchdog {
 636         pinctrl-names = "default";
 637         pinctrl-0 = <&watchdog_pins>;
 638         status = "okay";
 639 };
 640
 641 &wmac {
 642         mediatek,mtd-eeprom = <&factory 0x0000>;
 643         status = "okay";
 644 };